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MAX3691EVKIT-SO

MAX3691 Evaluation Kit

Maxim Integrated 

MAX3691 Evaluation Kit

Detailed Description

The MAX3691 evaluation kit (EV kit) operates from a

single +3.3V supply and includes the external compo-

nents necessary to observe the PECL serial-data output

on a 50Ωinput oscilloscope.

Each MAX3691 LVDS input (PCLKI+, PCLKI-, RCLK+,

RCLK-, PD_+, and PD_-) is internally terminated with a

100Ωdifferential input resistance. Ensure that LVDS

devices driving these inputs are not redundantly

terminated.

LVDS parallel-clock outputs (PCLKO+, PCLKO-) must

be differentially terminated with 100Ω.When terminating

these outputs into 50Ω loads, use AC coupling (see the

section Connecting Parallel-Clock LVDS Outputs to 50Ω

Input Oscilloscopes).

The EV kit serial-data output (SDO+, SDO-) termination

network allows the outputs to be connected directly to a

high-speed oscilloscope’s 50Ωinput. This termination pro-

vides the serial data outputs with a Thevenin equivalent

of 50Ωto VCC - 2V when connected to a 50Ωload. This

provides a 2-times output signal attenuation. If only one

of the serial data outputs is connected to an oscillo-

scope, ensure that the other is still properly terminated.

Keep in mind that the resistor networks at each output

provide proper termination only when they are terminat-

ed through 50Ωto ground. See the Alternative PECL

Output Termination section for other logic interfaces.

Table 1. Jumpers and Test Points

NAME TYPE DESCRIPTION NORMAL POSITION

JP1

2 pin

Disables the

loop filter

Open

JP3–JP7 2 pin

Jumper locations

(can be cut open

if necessary)

Shorted

Applications Information

Alternative PECL Output Termination

Alternative PECL output termination methods can be

used for different logic interfaces as long as they

provide a DC Thevenin equivalent of 50Ωto VCC - 2V.

For example, to interface SDO+ with a PECL or high-

impedance input, short resistors R2 and R3, and

replace R5 with an 82Ωresistor. To interface SDO+ with

ECL input test equipment, which is internally terminated

with 50Ωto -2V, take the following steps:

1) Remove R4 and R5.

2) Short R2 and R3.

3) Place a bias-T in series between the MAX3691 and

the test equipment. Connect the bias-T’s RF and

DC terminals to the SDO+ output and the RF termi-

nal to the test equipment’s ECL input. Then con-

nect the DC terminal to a VCC - 2V termination volt-

age through a 50Ωresistor.

Connecting Parallel-Clock LVDS

Outputs to 50ΩInput Oscilloscopes

To monitor the parallel-clock LVDS signals (PCLK0+,

PCLK0-) on a 50Ωinput oscilloscope, place a capacitor

or DC block in series with each output and the instru-

ment input. Do not connect MAX3691 outputs direct-

ly to 50Ωinputs or terminations to ground. Choose a

coupling capacitor (0.1µF recommended) large enough

in value to prevent pattern-dependent distortion of the

output signal.

2 _______________________________________________________________________________________

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