MB15C101PV1 Ver la hoja de datos (PDF) - Fujitsu

Número de pieza

componentes Descripción

Fabricante

MB15C101PV1

IF Band PLL Frequency Synthesizer

Fujitsu 

MB15C101

s FUNCTIONAL DESCRIPTIONS

Two different frequencies can be selected by Div input “H” or “L”.

The divide ratios are calculated using the following equation:

fVCO = {(P × N) + A} × fOSC ÷ R (A < N)

Symbol

fvco

fosc

N

A

P

R

Description

Output frequency of external VCO

Reference oscillation frequency

Divide ratio of the main counter

Divide ratio of the swallow counter

Preset divide ratio of dual modulus

prescaler

Divide ratio of the reference counter

Div = “H”

233.15 MHz

19.2 MHz

291

7

16/17

384 (fr = 50 kHz)

s PHASE DETECTOR TIME CHART

fr

Div = “L”

259.20 MHz

19.2 MHz

33

12

16/17

40 (fr = 480 kHz)

fp

tWU

tWL

LD

DO

High impedance

Note: • Phase error detection range: –2π to +2π

• Pulses on Do output signal during locked state are output to prevent dead zone.

• LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or

less and continues to be so for three cycles or more.

• tWU and tWL depend on OSCin input frequency.

tWU > 8/fosc (s) (e. g.tWU > 625.0ns, foscin = 12.8 MHz)

tWL < 16/fosc (s) (e. g. tWL < 1250.0ns, foscin = 12.8 MHz)

6

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