SPT7755B Ver la hoja de datos (PDF) - Signal Processing Technologies
Número de pieza
componentes Descripción
Fabricante
SPT7755B Datasheet PDF : 8 Pages
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OPERATION
The SPT7755 has 256 preamp/comparator pairs which are
each supplied with the voltage from VRT to VRB divided
equally by the resistive ladder as shown in the block diagram.
This voltage is applied to the positive input of each preampli-
fier/comparator pair. An analog input voltage applied at VIN is
connected to the negative inputs of each preamplifier/com-
parator pair. The comparators are then clocked through each
one's individual clock buffer. When the CLK pin is in the low
state, the master or input stage of the comparators compare
the analog input voltage to the respective reference voltage.
When the CLK pin changes from low to high the comparators
are latched to the state prior to the clock transition and output
logic codes in sequence from the top comparators, closest to
VRT (0 V), down to the point where the magnitude of the input
signal changes sign (thermometer code). The output of each
comparator is then registered into four 64-to-6 bit decoders
when the CLK is changed from high to low. At the output of the
decoders is a set of four 7-bit latches which are enabled
("track") when the clock changes from high to low. From here,
the output of the latches are coded into 6 LSBs from 4
columns and 4 columns are coded into 2 MSBs. Finally, 8
ECL output latches and buffers are used to drive the external
loads. The conversion takes one clock cycle from the input to
the data outputs.
Figure 2 - Timing Diagram
VIN
CLK
NCLK
DRA
NDRA
Data Bank A
DRB
NDRB
Data Bank B
Figure 3 - Subcircuit Schematics
INPUT CIRCUIT
AGND
VIN
VR
N
N+1
N+5
1.3 ns
N+2
N+4
N+3
N+6
N+7
1.4 ns typ
N-2
N
1.75 ns typ
N+2
N+4
1.4 ns typ
N-1
1.75 ns typ
N+1
N+3
OUTPUT CIRCUIT
AGND
DGND
CLOCK INPUT
AGND
CLK
CLK
VEE
SPT
Data Out
6
VEE
SPT7755
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