SPT7734 Ver la hoja de datos (PDF) - Signal Processing Technologies

Número de pieza

componentes Descripción

Fabricante

SPT7734

8-BIT, 40 MSPS,175 mW A/D CONVERTER

Signal Processing Technologies 

Figure 4 - Recommended Input Protection Circuit

+V

AVDD

Buffer

D1

47 Ω

D2

ADC

-V

D1 = D2 = Hewlett Packard HP5712 or equivalent

Figure 5 - On-Chip Protection Circuit

VDD

120 Ω

Analog

120 Ω

Pad

CLOCK INPUT

The SPT7734 is driven from a single-ended TTL-input clock.

Because the pipelined architecture operates on the rising edge of

the clock input, the device can operate over a wide range of input

clock duty cycles without degrading the dynamic performance.

DIGITAL OUTPUTS

The digital outputs (D0-D8) are driven by a separate supply

(OVDD) ranging from +3 V to +5 V. This feature makes it

possible to drive the SPT7734's TTL/CMOS-compatible out-

puts with the user's logic system supply. The format of the

output data (D0-D7) is straight binary. (See table III.) The

outputs are latched on the rising edge of CLK. These outputs

can be switched into a tri-state mode by bringing EN high.

Table III - Output Data Information

ANALOG INPUT

+F.S. + 1/2 LSB

OVERRANGE

D8

1

OUTPUT CODE

D7-D0

1111 1111

+F.S. -1/2 LSB

O

1111 111Ø

+1/2 F.S.

O

ØØØØ ØØØØ

+1/2 LSB

O

OOOO OOOØ

0.0 V

O

OOOO OOOO

(Ø indicates the flickering bit between logic 0 and 1).

DO NOT CONNECT PINS (DNC)

There are two pins designated as Do Not Connect (DNC).

These pins must be left floating for proper operation of the

device.

OVERRANGE OUTPUT

The OVERRANGE OUTPUT (D8) is an indication that the

analog input signal has exceeded the positive full scale input

voltage by 1 LSB. When this condition occurs, D8 will switch

to logic 1. All other data outputs (D0 to D7) will remain at

logic 1 as long as D8 remains at logic 1. This feature makes

it possible to include the SPT7734 into higher resolution

systems.

SPT

7

SPT7734

1/27/98

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