M62334FP(2007) Ver la hoja de datos (PDF) - Renesas Electronics

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M62334FP
(Rev.:2007)

8-bit 4ch I2C BUS D/A Converter with Buffer Amplifiers

Renesas Electronics 

M62334P/FP, M62339P/FP

I2C BUS Line Characteristics

Item

Symbol

Min.

Max.

Unit

SCL clock frequency

Time the bus must be free before a new transmission can start

Hold time START condition

(After this period, the first clock pulse is generated)

fSCL

tBUF

tHD:STA

0

100

kHz

4.7

—

µs

4.0

—

µs

Low period of the clock

High period of the clock

Set-up time for START condition

(Only relevant for a repeated START condition)

tLOW

tHIGH

tSU:STA

4.7

—

µs

4.0

—

µs

4.7

—

µs

Hold time DATA

tHD:DAT

0

—

µs

Set-up time DATA

Rise time of both SDA and SCL lines

tSU:DAT

tR

250

—

ns

—

1000

ns

Fall time of both SDA and SCL lines

Set-up time for STOP condition

tF

tSU:STO

—

300

ns

4.0

—

µs

Note: Transmitter must internally provide at least a hold time to bridge the undefined region (300 ns Max) of the falling

edge of SCL.

Timing Chart

VIH

SDA

VIL

tHD:STA

tR, tF

tSU:DAT

tHD:DAT

tSU:STA

tBUF

tSU:STO

VIH

SCL

VIL

Start

tLOW

tHIGH

Start

Stop

Start

REJ03D0866-0300 Rev.3.00 Jun 15, 2007

Page 4 of 9

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