HI1172 Ver la hoja de datos (PDF) - Intersil
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HI1172 Datasheet PDF : 7 Pages
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HI1172
Digital Output
Notes On Operation
Compatibility between analog input voltage and the digital
output code is indicated in the chart below.
INPUT SIGNAL
VOLTAGE
VRT
•
•
•
•
•
•
•
•
VRB
STEP
0
•
•
•
31
32
•
•
•
63
DIGITAL OUTPUT CODE
MSB
LSB
1 1111 1
•
•
•
1 0000 1
0 1111 1
•
•
•
0 0000 0
Operation (See Block Diagram and Waveform)
The HI1172 is a 2-step parallel system A/D converter
featuring a 3-bit upper comparators group and 2 lower com-
parators groups of 3-bit each. The reference voltage that is
equal to the voltage between VRT-VRB/8 is constantly
applied to the upper 3-bit comparator block. Voltage that cor-
responded to the upper data is fed through the reference
supply to the lower data.
This IC uses an offset cancel type comparator and operates
synchronously with an external clock. It features the follow-
ing operating modes which are respectively indicated on the
timing chart with S, H, C symbols, i.e., input sampling (auto
zero) mode, input hold mode and comparison mode.
• VDD , VSS - To reduce noise effects, separate the analog
and digital systems close to the device. For both the digital
and analog VDD pins, use a ceramic capacitor of about
0.1µF set as close as possible to the pin to bypass to the
respective GNDs.
• Analog Input - Compared with a flash type A/D converter,
the input capacitance of the analog input is rather small.
However it is necessary to drive with an amplifier featuring
sufficient bandwidth and drive capability. When driving
with an amplifier of low output impedance, parasitic oscil-
lation may occur. That may be prevented by inserting a
resistance of about 100Ω in series between the amplifier
output and A/D input.
• Clock Input - The clock line wiring should be as short as
possible. Also, to avoid any interference with other signals,
separate it from the other circuits.
• Reference Input - Voltage between VRT to VRB is compat-
ible with the dynamic range of the analog input. By
bypassing VRT and VRB pins to GND with a capacitor of
about 0.1µF, stable characteristics are obtained.
• Timing - Analog input is sampled with the falling edge of
CLK and output as digital data with a delay of 2.5 clocks
and with the following rising edge. The delay from the
clock rising edge to the data output is about 18ns.
• About Latch Up - It is necessary that AVDD and DVDD pins
to be the common source of power supply. This is to avoid
latch up due to the voltage difference between AVDD and
DVDD pins when power is ON.
The operation of respective parts is as indicated in the chart.
Input voltage Vi (1) is sampled with the falling edge of the
first clock by means of the upper comparator block and the
lower comparator A block.
The upper comparators block finalizes comparison data MD
(1) with the rising edge of the first clock. simultaneously the
reference supply generates the lower reference voltage RV
(1) that corresponded to the upper results. The lower com-
parator block finalizes comparison data LD (1) with the rising
edge of the second clock. MD (1) and LD (1) are combined
and output as Out (1) with the rising edge of the 3rd clock.
Accordingly there is a 2.5 clock delay from the analog input
sampling point to the digital data output.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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