Functional Diagram
HM-6642/883
A8
A
A7
A6
LATCHED
6
GATED
ADDRESS
ROW
A5
A4
REGISTER
A
DECODER
64
A3
6
64 x 64
MATRIX
ALL LINES POSITIVE LOGIC - ACTIVE HIGH
THREE STATE BUFFERS:
A HIGH
OUTPUT ACTIVE
A
A2
A1
A0
LATCHED
ADDRESS
REGISTER
3
A
3
88 8888 8 8
GATED COLUMN
DECODER
D
DATA LATCHES:
L HIGH
Q=D
Q LATCHES ON RISING EDGE OF E
ADDRESS LATCHES AND GATED DECODERS:
LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF E
P SHOULD BE HARDWIRED TO GND EXCEPT
DURING PROGRAMMING
E
8-BIT DATA LATCH
G1
G2
G3
Q0 Q1 Q2 Q3
Q4
Q5 Q6 Q7
2