IDT70V05L(1996) Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT70V05L
(Rev.:1996)

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V05S/L

HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

TIMING WAVEFORM OF SLAVE WRITE (M/S = VIL)

tWP

W R/ "A"

BUSY"B"

tWB( 3 )

W R/ "B"

(2)

COMMERCIAL TEMPERATURE RANGE

tWH ( 1 )

2941 drw 14

WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1)

ADDR"A"

and "B"

ADDRESSES MATCH

CE"A"

tAPS (2)

CE"B"

tBAC

BUSY"B"

tBDC

2941 drw 15

WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING

(M/S = VIH)(1)

ADDR"A"

ADDRESS "N"

tAPS (2)

ADDR"B"

BUSY"B"

MATCHING ADDRESS "N"

tBAA

tBDA

2941 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.

6.35

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