IDT70V07L(1996) Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT70V07L Datasheet PDF : 18 Pages
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IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
PIN CONFIGURATIONS (1,2)
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 450mW of power.
The IDT70V07 is packaged in a ceramic 68-pin PGA, a 68-
pin PLCC, and a 80-pin thin plastic quad flatpack (TQFP).
INDEX
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
IDT70V07
55
16
J68-1
54
17
53
18
PLCC
52
19
TOP
51
20
VIEW(3)
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
2943 drw 02
INDEX
N/C 1
I/O2L
2
I/O3L
3
I/O4L
4
I/O5L
5
GND 6
I/O6L
7
I/O7L
8
VCC
9
N/C 10
GND 11
I/O0R 12
I/O1R 13
I/O2R 14
VCC 15
I/O3R 16
I/O4R 17
I/O5R 18
I/O6R 19
N/C 20
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate the actual part marking.
6.37
70V07
PN80-1
TQFP
TOP
VIEW(3)
60 N/C
59 A5L
58 A4L
57 A3L
56 A2L
55 A1L
54 A0L
53
INTL
52 BUSYL
51 GND
50 M/S
49 BUSYR
48
INTR
47 A0R
46 A1R
45 A2R
44 A3R
43 A4R
42 N/C
41 N/C
2943 drw 03
2
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