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CDP1823C/3 Ver la hoja de datos (PDF) - Intersil

Número de pieza
componentes Descripción
Fabricante
CDP1823C/3 Datasheet PDF : 6 Pages
1 2 3 4 5 6
CDP1823C/3
VDD
DATA RETENTION
MODE
0.95 VDD
0.95 VDD
VDR
tCDR
tf
tr
tRC
CS
VIH
VIL
VIH
VIL
FIGURE 3. LOW VDD DATA RETENTION WAVEFORMS
R
1
A15
2
3
R
4
A14
5
6
R
7
A13
8
A12
9
A11
10
A10
11
12
R = 10kΩ ±20%
24
VDD
23
A0
22
A1
21
A2
20
A3
19
A4
18
A5
17
A6
16
01
15
A7
14
A8
13
A9
PACKAGE TEMPERATURE DURATION
VDD
D
125oC
160 Hrs
7V
0
01
A0
A1
1.6 2.2 5.0
6.6 7.2
10.0
VDD
0
VDD
0
VDD
0
NOTE:
1. A1 - A11 are division by 2 based on A0.
FIGURE 4. DYNAMIC/OPERATING BURN-IN CIRCUIT AND TIMING DIAGRAM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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