ATF2500C Ver la hoja de datos (PDF) - Atmel Corporation

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ATF2500C

ATF2500C CPLD Family Datasheet

Atmel Corporation 

Figure 8-2. I/O Diagram

INPUT

PROGRAMMABLE

OPTION

9. Functional Logic Diagram Description

The ATF2500C functional logic diagram describes the interconnections between the input, feed-

back pins and logic cells. All interconnections are routed through the single global bus.

The ATF2500Cs are straightforward and uniform PLDs. The 24 macrocells are numbered 0

through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five

lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous reset

and clock per flip-flop, and an output enable. The top 12 product terms are grouped into three

sum terms, which are used as shown in the macrocell diagrams.

Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share

Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing

Preset 7.

The 14 dedicated inputs and their complements use the numbered positions in the global bus as

shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2(1) true

and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by these

signals in the global bus are the six numbers in the bus diagram next to each macrocell.

Note: 1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATF2500Cs.

8 ATF2500C

0777K–PLD–1/24/08

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