ATF2500C Ver la hoja de datos (PDF) - Atmel Corporation
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ATF2500C Datasheet PDF : 24 Pages
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The ATF2500C is organized around a single universal array. All pins and feedback terms are
always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out-
puts of each flip-flop.
In the ATF2500C, four product terms are input to each sum term. Furthermore, each macrocell’s
three sum terms can be combined to provide up to 12 product terms per sum term with no per-
formance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing
further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combina-
torial feedback to the logic array.
Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops
may also be individually configured to have direct input pin clocking. Each output has its own
enable product term. Eight synchronous preset product terms serve local groups of either four or
eight flip-flops. Register preload functions are provided to simplify testing. All registers automati-
cally reset upon power-up.
2. Pin Configurations
Table 2-1.
Pin Name
IN
CLK/IN
I/O
I/O 0,2,4...
I/O 1,3,5...
GND
VCC
Pin Configurations
Function
Logic Inputs
Pin Clock and Input
Bi-directional Buffers
Even I/O Buffers
Odd I/O Buffers
Ground
+5V Supply
Figure 2-1. DIP
CLK/IN 1
IN 2
IN 3
I/O0 4
I/O1 5
I/O2 6
I/O3 7
I/O4 8
I/O5 9
VCC 10
I/O17 11
I/O16 12
I/O15 13
I/O14 14
I/O13 15
I/O12 16
IN 17
IN 18
IN 19
IN 20
40 IN
39 IN
38 IN
37 IN
36 I/O6
35 I/O7
34 I/O8
33 I/O9
32 I/O10
31 I/O11
30 GND
29 I/O23
28 I/O22
27 I/O21
26 I/O20
25 I/O19
24 I/O18
23 IN
22 IN
21 IN
Figure 2-2. PLCC
I/O2 7
I/O3 8
I/O4 9
I/O5 10
VCC 11
VCC 12
I/O17 13
I/O16 14
I/O15 15
I/O14 16
I/O13 17
39 I/O7
38 I/O8
37 I/O9
36 I/O10
35 I/O11
34 GND
33 GND
32 I/O23
31 I/O22
30 I/O21
29 I/O20
Note:
(PLCC package) pin 4 and pin 26 GND connections are
not required, but are recommended for improved noise
immunity.
2 ATF2500C
0777K–PLD–1/24/08
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