tR C
Address
tAA
Data Out
tOHA
Previous Data Valid
Assumptions:
1.R/W is HIGH for read cycle
2.Device is continuously selected CE =LOW and OE=LOW
Figure 3a. Read Cycle 1
Data Valid
CE
OE
Data Out
tACE
tDOE
tLZOE
tLZCE
tHZCE
tHZOE
Assumptions:
1. Address valid prior to or coincident with CE transition LOW
2. R/W is HIGH for read cycle
Figure 3b. Read Cycle 2
Address
R/WR
DataINR
AddressL
DATAOUTL
Assumptions:
1. BUSY = HIGH for the writing port
2. CE L = C ER = LOW
tWC
M A TC H
tPWE
tH D
tS D
VALID
M A TC H
tD D D
tWDD
VALID
Figure 3c. Read Timing with Port-to-Port Delay
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