KSZ8051MNLI Ver la hoja de datos (PDF) - Micrel

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Fabricante

KSZ8051MNLI

10Base-T/100Base-TX Physical Layer Transceiver

Micrel 

Micrel, Inc.

KSZ8051MNL/RNL

List of Figures

Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 21

Figure 2. KSZ8051MNL MII Interface .................................................................................................................................. 23

Figure 3. KSZ8051RNL RMII Interface (25MHz Clock Mode) ............................................................................................ 26

Figure 4. KSZ8051RNL RMII Interface (50MHz Clock Mode) ............................................................................................ 26

Figure 5. KSZ8051MNL/RNL and KSZ8041FTL Back-to-Back Media Converter ............................................................... 27

Figure 6. Typical Straight Cable Connection ....................................................................................................................... 29

Figure 7. Typical Crossover Cable Connection ................................................................................................................... 30

Figure 8. KSZ8051MNL/RNL Power and Ground Connections........................................................................................... 33

Figure 9. MII SQE Timing (10Base-T) ................................................................................................................................. 46

Figure 10. MII Transmit Timing (10Base-T) ......................................................................................................................... 47

Figure 11. MII Receive Timing (10Base-T) .......................................................................................................................... 48

Figure 12. MII Transmit Timing (100Base-TX)..................................................................................................................... 49

Figure 13. MII Receive Timing (100Base-TX)...................................................................................................................... 50

Figure 14. RMII Timing – Data Received from RMII ............................................................................................................ 51

Figure 15. RMII Timing – Data Input to RMII ....................................................................................................................... 51

Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 52

Figure 17. MDC/MDIO Timing.............................................................................................................................................. 53

Figure 18. Reset Timing....................................................................................................................................................... 54

Figure 19. Recommended Reset Circuit.............................................................................................................................. 55

Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output...................................................... 55

Figure 21. Reference Circuits for LED Strapping Pins......................................................................................................... 56

Figure 22. 25MHz Crystal / Oscillator Reference Clock Connection ................................................................................... 57

Figure 23. 50MHz Oscillator Reference Clock Connection ................................................................................................. 58

July 2010

7

M9999-070910-1.0

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