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V96SSC

HIGH-INTEGRATION SYSTEM CONTROLLER FOR i960 Sx/Jx AND PowerPC™ 401Gx PROCESSORS

QuickLogic Corporation 

V96SSC

accommodated due to the V96SSC’s flexibility.

Two DRAM banks are provided. Each bank has its own programmable address base and size. The

mapping of memory address lines to row and column addresses is also programmable for each bank.

The twelve mixed address lines (MA[11:0]) are shared by both banks. Each bank may be

independently enabled and/or write protected. Both banks share a common DRAM signal timing

generator that controls all DRAM timing parameters. DRAM array width can be set to either 16-bit or

32-bits; the V96SSC controls lane steering logic in mixed width systems.

FPM, EDO, and Ramtron EDRAMs are a natural fit for burst bus processors such as i960 or

PPC401Gx family. The V96SSC takes advantage of fast page mode accesses for every burst

transaction, insuring the highest transfer rate possible. The V96SSC also supports extended burst

peripherals, such as networking controllers, up to a maximum length of 64Byte data cycles.

The DRAM controller also includes page cache management logic. This logic detects subsequent

burst accesses within the same DRAM page, and eliminates the RAS precharge time and row address

cycles for these accesses. Removing these cycles can reduce the average wait-state profile for many

applications. The “aggressiveness” of the caching algorithm is programmable, and page caching can

be completely disabled. The page size is programmable from 512 to 8192 bytes.

2.3 DMA Controller

Two independent DMA Channels are provided in the V96SSC. The DMA Controller generates fly-by

cycles to transfer data directly from the DRAM to the selected peripheral, or vice-versa. Each channel

includes a request input (DREQx), an acknowledge output (DACKx), and an end-of-process output

(EOPx, accessible via the I/O Multiplexer). Each channel can also be assigned to a chip select/strobe

channel to provide the necessary strobing signals to the DMA target/source peripheral.

The DMA buffer start and stop addresses are programmable, as is the direction of transfer (read or

write). Transfers may be initiated either via the DREQx pins or through software.

The DMA Controller’s programmable throttle count allows long transfers to be periodically interrupted

to allow the processor access to the bus for code fetches, etc.

2.4 Serial Communications Unit (SCU)

The V96SSC’s Serial Communications Unit offers both synchronous and asynchronous modes. In

asynchronous mode, the Serial Communications Unit functions as an industry standard, full duplex

UART. Transmission and reception are double buffered to help prevent data overruns. Interrupts are

generated on receiver buffer full, transmit buffer empty, buffer overrun error, and framing error.

In synchronous (SPI) mode, data is moved into, or out of, the SCU’s buffers on transitions of the serial

clock output pin (SCLK). Data word length is programmable from 1 to 16 bits. An interrupt is generated

upon completion of an SPI transfer. SPI mode is ideal for connecting to serial interface peripherals

such as A/D converters.

The clock reference for the Serial Communications Unit can be either the independent baud rate

generator or general purpose timer 1.

2.5 Chip Select/Strobe Unit

The Chip Select/Strobe Unit provides all the logic necessary to interface a wide array of peripherals

and memory components to the i960Sx/Jx processor. Address decoding, wait-state generation, chip-

select, and read/write strobe generation are handled completely by the V96SSC; no glue logic is

Copyright © 1997, V3 Semiconductor Inc.

V96SSC Data Sheet Rev 2.3

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