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M34S32

32K Serial I2C Bus EEPROM With User-Defined Read-Only Block and 32-Byte OTP Page

STMicroelectronics 

M34S32

DESCRIPTION (cont’d)

The memory is compatible with the I2C extended

addressing standard, two wire serial interface

which uses a bi-directional data bus and serial

clock. The memory carries a built-in 4 bit, unique

device identification code (1010) corresponding to

the I2C bus definition. The memory behaves as

slave devices in the I2C protocol with all memory

operations synchronized by the serial clock. Read

and write operations are initiated by a START con-

dition generated by the bus master. The START

condition is followed by the Device Select Byte.

This is a stream of 4 bits (the identification code

1010), then 3 bits of memory block access input,

plus one read/write bit. The byte is finally terminat-

ed by an acknowledge bit.

The M34S32 contains three memory blocks: the

OTP page, the EEPROM block and the ROM

block. The OTP (One Time Programmable) page

is a page of 32 bytes, written once by the user. The

OTP page is not located within the 32 Kbits EEP-

ROM area. Once written, the OTP page cannot be

modified by further write instructions. The ROM

block resides inside the 32 Kbit EEPROM area.

The size of the ROM block is defined (by the user)

with the help of the Control Register.

The OTP page is accessed with the Device Select

Byte 1010001x, the EEPROM and ROM blocks

are accessed with the Device Select Byte

1010000x. The control register is accessed with

the Device Select Byte 1010100x (see Table 3).

Table 3. Device Select Byte

When writing data to the memory it responds to

the 8 bits received by asserting an acknowledge

bit during the 9th bit time. When data is read by the

bus master, it acknowledges the receipt of the

data bytes in the same way.

Data transfers are terminated with a STOP condi-

tion.

Power On Reset: VCC lock out write protect. In

order to prevent data corruption and inadvertent

write operations during power up, a Power On Re-

set (POR) circuit is implemented. Until the VCC

voltage has reached the POR threshold value, the

internal reset is active: all operations are disabled

and the device will not respond to any command.

In the same way, when VCC drops down from the

operating voltage to below the POR threshold val-

ue, all operations are disabled and the device will

not respond to any command. A stable VCC must

be applied before applying any logic signal.

SIGNAL DESCRIPTION

Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A

resistor can be connected from the SCL line to

VCC to act as a pull up (see Figure 3)

Serial Data (SDA). The SDA pin is bi-directional

and is used to transfer data in or out of the memo-

ry. It is an open drain output that may be wire-

OR’ed with other open drain or open collector sig-

nals on the bus. A pull-up resistor must be con-

nected from the SDA bus line to VCC (see Figure

3).

Device Code

Memory Block Access

RW

Device Select Bit

b7

b6

b5

b4

b3

b2

b1

b0

EEPROM and ROM access

1

0

1

0

0

0

0

RW

OTP Page access

1

0

1

0

0

0

1

RW

Control Register access

1

0

1

0

1

0

0

RW

Table 4. Operating Modes

Mode

RW bit

Current Address Read

1

0

Random Address Read

1

Sequential Read

1

Byte Write

0

Page Write

0

Data

Bytes

1

1

≥1

1

≤ 32

Initial Sequence

START, Device Select, RW = 1

START, Device Select, RW = 0, Address

reSTART, Device Select, RW = 1

As CURRENT or RANDOM Mode

START, Device Select, RW = 0

START, Device Select, RW = 0

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