AD9875-EB Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD9875-EB Datasheet PDF : 24 Pages
| |||
AD9875–SPECIFICATIONS (continued)
Parameter
Tx PATH INTERFACE
Maximum Input Nibble Rate, 2× Interp.
Tx-Set Up Time (tSU)
Tx-Hold Time (tHD)
Rx PATH INTERFACE
Maximum Output Nibble Rate
Rx-DataValid Time (tVT)
Rx-Data Hold Time (tHT)
CMOS LOGIC INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
Logic “1” Voltage
Logic “0” Voltage
Digital Output Rise/Fall Time
POWER SUPPLY
All Blocks Powered Up
IS_TOTAL (Total Supply Current)
IS_TOTAL (Tx_QUIET Pin Asserted)
Digital Supply Current (IDRVDD + IDVDD)
Analog Supply Current (IAVDD)
Power Consumption of Functional Blocks:
Rx LPF
ADC and FPGA
Rx Reference
Interpolator
DAC
PLL-B
PLL-A
Voltage Regulator Controller
All Blocks Powered Down
Supply Current IS, fOSCIN = 32 MHz
Supply Current IS, fOSCIN Idle
Power Supply Rejection
Tx Path (∆VS = Ϯ10%)
Rx Path (∆VS = Ϯ10%)
SERIAL CONTROL BUS
Maximum SCLK Frequency (fSCLK)
Clock Pulsewidth High (tPWH)
Clock Pulsewidth Low (tPWL)
Clock Rise/Fall Time
Data/Chip-Select Setup Time (tDS)
Data Hold Time (tDH)
Data Valid Time (tDV)
RECEIVE-TO-TRANSMIT ISOLATION
(10 MHz, Full-Scale Sinewave Output/Output)
Isolation: Tx Path to Rx Path, Gain = +36 dB
Isolation: Rx Path to Tx Path, Gain = –6 dB
VOLTAGE REGULATOR CONTROLLER
Output Voltage (VFB with SI2301 Connected)
Line Regulation (∆VFB%/∆VDVDD% × 100%)
Load Regulation (∆VFB/∆ILOAD)
Maximum Load Current (ILOAD)
Specifications subject to change without notice.
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Test
Level
II
II
II
I
II
II
II
II
II
II
III
II
II
II
Full
I
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
Full
II
Full
II
25°C
III
25°C
III
Full
II
Full
II
Full
II
Full
II
Full
II
Full
II
Full
II
25°C
III
25°C
III
Full
I
25°C
III
25°C
III
Full
II
–4–
Min
Typ
128
3.0
0
110
1.5
VDRVDD – 0.7
3
VDRVDD – 0.6
1.5
262
172
77
185
110
55
2
33
18
8
24
1
19
10
62
54
25
18
18
25
0
–75
–70
1.25
1.30
100
60
250
Max
3.0
0.4
12
12
0.4
2.5
288
22
12
1
20
1.35
Unit
MHz
ns
ns
MHz
ns
ns
V
V
µA
µA
µF
V
V
ns
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
dB
dB
MHz
ns
ns
ms
ns
ns
ns
dB
dB
V
%
mΩ
mA
REV. 0
Share Link: 