WED9LC6816V Ver la hoja de datos (PDF) - White Electronic Designs Corporation
Número de pieza
componentes Descripción
Fabricante
WED9LC6816V Datasheet PDF : 27 Pages
| |||
White Electronic Designs
WED9LC6816V
Output Functional Descriptions
Symbol
SSCK#
SSADS#
SSOE#
SSWE#
SSCE#
SDCK#
SDCE
SDRAS#
SDCAS#
SDWE#
A0-17
SDA10
DQ0-31
BWE0-3
VCC, VSS
VCCQ
Type Signal
Polarity Function
Input Pulse Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
Input
Input
Input
Input
Pulse
Pulse
Pulse
Pulse
Active Low
When sampled at the positive rising edge of the clock, SSADS#, SSOE#, and SSWE# define
the operation to be executed by the SSRAM.
Active Low SSCE# disable or enable SSRAM device operation.
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Active Low SDCE disable or enable device operation by masking or enabling all inputs except SDCK# and BWE0-3.
Input Pulse
Input Level
Input
Output
Input
Supply
,Supply
Level
Pulse
Active Low
—
—
When sampled at the positive rising edge of the clock, SDCAS#, SDRAS#, and SDWE#
define the operation to be executed by the SDRAM.
Address bus for SSRAM and SDRAM
A0 and A1 are the burst address inputs for the SSRAM
During a Bank Active command cycle, A0-11, SDA10 defines the row address (RA0-10) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when
sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke
Autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA10 is high,
autoprecharge is selected and A12 and A13 define the bank to be precharged. If SDA10 is low,
autoprecharge is disabled.
During a Precharge command cycle, SDA10 is used in conjunction with A12 and A13 to control
which bank(s) to precharge. If SDA10 is high, all banks will be precharged regardless of
the state of A12 and A13. If SDA10 is low, then A12 and A13 are used to define which bank to
precharge.
Data Input/Output are multiplexed on the same pins.
BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM BWE0 is
associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31.
Power and ground for the input buffers and the core logic.
Data base power supply pins, 3.3V (2.5V future).
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Share Link: 