LTC694IN8-3.3-PBF Ver la hoja de datos (PDF) - Linear Technology
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LTC694IN8-3.3-PBF Datasheet PDF : 20 Pages
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LTC694-3.3/LTC695-3.3
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, VBATT = 2V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power-Fail Detector
PFI Input Threshold
l
1.25
1.3
1.35
V
PFI Input Threshold PSRR
0.3
mV/V
PFI Input Current
PFO Output Voltage (Note 4)
PFO Short-Circuit Source Current (Note 4)
PFI Comparator Response Time (Falling)
PFI Comparator Response Time (Rising) (Note 4)
ISINK = 800μA
ISOURCE = 0.1μA
PFI = HIGH, PFO = 0V
PFI = LOW, PFO = VOUT
ΔVIN = –20mV, VOD = 15mV
ΔVIN = 20mV, VOD = 15mV
with 10kΩ Pull-Up
l
±0.01
±25
nA
l
l
2.3
0.3
V
V
l
1
3
25
μA
17
μA
2
μs
40
μs
8
μs
Chip Enable Gating
CE IN Threshold
CE IN Pull-Up Current (Note 6)
CE OUT Output Voltage
CE IN Propagation Delay
CE OUT Output Short-Circuit Current
VIL
VIH
ISINK = 800μA
ISOURCE = 400μA
ISOURCE = 1μA, VCC = 0V
CL = 20pF
Output Source Current
Output Sink Current
0.45
V
1.9
V
3
μA
l
l VOUT – 0.50
l VOUT – 0.05
0.3
V
V
V
l
30
50
ns
15
mA
20
mA
Oscillator
OSC IN Input Current (Note 6)
±2
μA
OSC SEL Input Pull-Up Current (Note 6)
5
μA
OSC IN Frequency Range
OSC SEL = 0V
OSC SEL = 0V, CA = 47pF
l
0
125
kHz
4
kHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: For military temperature range par_ts, consult the factory.
Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and
RESET have weak internal pull-ups of typically 3μA. However, external pull-
up resistors may be used when higher speed is required.
Note 5: The external clock feeding into the circuit passes through the
oscillator before clocking the watchdog timer. Variation in the timeout
period is caused by phase errors which occur when the oscillator divides
the external clock by 64. The resulting variation in the timeout period is 64
plus one clock of jitter.
Note 6: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pull-ups which pull to the supply when the input pins are floating.
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5
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