AS4LC256K16E0-35JC Ver la hoja de datos (PDF) - Alliance Semiconductor
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AS4LC256K16E0-35JC Datasheet PDF : 25 Pages
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AS4LC256K16EO
®
Functional description
The AS4LC256K16EO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as
262,144 words by 16 bits. The AS4LC256K16EO is fabricated with advanced CMOS technology and designed with innovative
design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.
The AS4LC256K16EO features a high speed page mode operation in which high speed read, write and read-write are
performed on any of the 512 × 16 bits defined by the column address. The asynchronous column address uses an extremely
short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Very fast CAS
to output access time eases system design.
Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the
following:
• RAS-only refresh cycles
• Hidden refresh cycles
• CAS-before-RAS refresh cycles
• Normal read or write cycles
• Self refresh cycles
The AS4LC256K16EO is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely
available automated testing and insertion equipment. System level features include single power supply of 3.3V ± 0.3V
tolerance and direct interface with TTL logic families.
Logic block diagram
VCC
GND
COLUMN DECODER
SENSE AMP
DATA
I/O
BUFFER
I/O0 to I/O15
A0
A1
A2
RAS
RAS CLOCK
GENERATOR
A3
A4
A5
A6
A7
UCAS
CAS CLOCK
GENERATOR
A8
LCAS
WE CLOCK
WE
GENERATOR
512×512×16
ARRAY
(4,194,304)
OE
SUBSTRATE
BIAS
GENERATOR
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Symbol
Min
Typ
VCC
3.0
3.3
GND
0.0
0.0
VIH
2.0
–
VIL
–1.0
–
(Ta = 0°C to +70°C)
Max
Unit
3.6
V
0.0
V
VCC + 1
V
0.8
V
4/11/01; V.1.1
Alliance Semiconductor
P. 2 of 25
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