AZ100ELT21 Ver la hoja de datos (PDF) - Unspecified
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AZ100ELT21 Datasheet PDF : 5 Pages
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AZ100ELT21
ARIZONA MICROTEK, INC.
Differential PECL to CMOS/TTL Translator
FEATURES
• 3.5ns Typical Propagation Delay
• Differential PECL Inputs
• CMOS/TTL Outputs
• Flow Through Pinouts
• Operating Range of 3.0V to 5.5V
• Direct Replacement for ON Semiconductor
MC100ELT21
• Use AZ100ELT21 for 10K Applications
DESCRIPTION
PACKAGE AVAILABILITY
PACKAGE
SOIC 8
SOIC 8 T&R
SOIC 8 T&R
TSSOP 8
TSSOP 8 T&R
TSSOP 8 T&R
PART NO.
AZ100ELT21D
AZ100ELT21DR1
AZ100ELT21DR2
AZ100ELT21T
AZ100ELT21TR1
AZ100ELT21TR2
MARKING
AZM100ELT21
AZM100ELT21
AZM100ELT21
AZHLT21
AZHLT21
AZHLT21
The AZ100ELT21 is a differential PECL to CMOS/TTL translator. Because PECL (Positive ECL) levels are
used, only VCC and ground are required. The small outline 8-lead packaging and the single gate of the ELT21 makes
it ideal for those applications where space, performance and low power are at a premium.
The ELT21 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device.
For single-ended input applications, the VBB reference should be connected to one side of the D0/D¯¯0 differential
input pair. The input signal is then fed to the other D0/D¯¯0 input. The VBB pin should be used only as a bias for the
ELT21 as its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01µF
capacitor.
NOTE: Specification in ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION
PIN
Q
D0, D¯¯0
VCC
VBB
GND
NC
FUNCTION
CMOS/TTL Output
Differential Inputs
Positive Supply
Reference Voltage Output
Ground
No Connect
NC 1
D0 2
PECL
D0 3
VBB 4
8 VCC
CMOS/TTL
7Q
6 NC
5 GND
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
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