MAS9122 Ver la hoja de datos (PDF) - Unspecified
Número de pieza
componentes Descripción
Fabricante
MAS9122 Datasheet PDF : 12 Pages
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DA9122.002
7 September, 2001
x Load Regulation
Parameter
Load Regulation LDO_A
Load Regulation LDO_B
Load Regulation LDO_C
x Line Regulation
Symbol
Conditions
0 mA < IOUT < 135 mA
0 mA < IOUT < 100 mA
0 mA < IOUT < 70 mA
0 mA < IOUT < 50 mA
Min Typ Max Unit
22 50 mV
22 30
21 25 mV
13 22 mV
Parameter
Line Regulation for all LDOs
x PSRR
Symbol
Conditions
Min Typ Max Unit
IOUT = IMAX ,VIN from 5.3 V to 3.1 V
0.40 1.2 mV
Parameter
PSRR for all LDOs
Symbol
Conditions
IOUT = Max IOUT
VIN = 3.6 V
f = 1 kHz
f = 10 kHz
Min Typ Max Unit
dB
75
47 63
x Noise and Crosstalk
Parameter
Noise Voltage for all LDOs
Symbol
VNO
Conditions
100 Hz < f < 100 kHz
Min Typ Max Unit
25 30 µVrms
x Dynamic Parameters
Parameter
Symbol
Conditions
Min Typ Max Unit
Start-up Delay (from enabling
LDO_A to 90% * VOUT(NOM) ,
other LDOs at ON state)
(Note 2)
VENA from < 0.3 V to > 2.0 V,
25
µs
VENBC > 2.0 V, IOUT = Max IOUT,
COUTA = 1 µF
Overshoot
VENA from < 0.3 V to > 2.0 V,
1
%
VENBC > 2.0 V, IOUT = Max IOUT,
COUTA = 1 µF
Settling Time
VENA from < 0.3 V to > 2.0 V,
200
µs
(from 90% * VOUT(NOM)A to max
VENBC > 2.0 V, IOUT = Max IOUT,
±0.1% fluctuation)
COUTA = 1 µF, w/o CBYPASS
Note 2: When all regulators are disabled the start-up delay is a function of a bypass capacitor. Typically 0.5 ms for 10 nF capacitor.
TRL
VOUT
50%
overshoot
90%
start-up delay
settling time
Figure 1. Definitions of
start-up delay, overshoot
and settling time.
5 (12)
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