AD7776 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD7776 Datasheet PDF : 12 Pages
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AD7776/AD7777/AD7778
TIMING SPECIFICATIONS1, 2
(VCC = +5 V ؎ 5%; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.)
Parameter
Label Limit at TMIN to TMAX Unit
Test Conditions/Comments
INTERFACE TIMING
CS Falling Edge to WR or RD Falling Edge t1
WR or RD Rising Edge to CS Rising Edge
t2
WR Pulsewidth
t3
CS or RD Active to Valid Data3, 4
t4
Bus Relinquish Time after RD3, 5
t5
Data Valid to WR Rising Edge
t6
Data Valid after WR Rising Edge
t7
WR Rising Edge to BUSY Falling Edge
t8
WR Rising Edge to BUSY Rising Edge or
INT Falling Edge
t9
t10
WR or RD Falling Edge to INT Rising Edge t11
0
0
53
60
10
45
55
10
1.5 tCLKIN
2.5 tCLKIN + 70
19.5 tCLKIN + 70
33.5 tCLKIN + 70
60
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns max
ns max
ns max
ns max
Timed from Whichever Occurs Last
CR9 = 0
Single Conversion, CR6 = 0
Double Conversion, CR6 = 1
CR9 = 1
NOTES
1See Figures 1 to 3.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3100% production tested. All other times are guaranteed by design, not production tested.
4t4 is measured with the load circuit of Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5t5 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured time is then extrapolated back
to remove the effects of charging or discharging the 100 pF capacitor. This means that the time t 5 quoted above is the true bus relinquish time of the device and, as
such, is independent of the external bus loading capacitance.
Specifications subject to change without notice.
t1
t2
CS
RD
t4
t5
DB0–DB9
Figure 1. Read Cycle Timing
WR, RD
BUSY
(CR8 = 0)
INT
(CR8 = 1)
t3
t8
FIRST
CONVERSION
FINISHED
(CR6 = 0)
t9
SECOND
CONVERSION
FINISHED (CR6 = 1)
AD7777/AD7778 ONLY
t11
t10
t9
t10
Figure 3. BUSY/INT Timing
t1
CS
WR
DB0–DB9
t3
t6
t2
t7
Figure 2. Write Cycle Timing
IOL
1.6mA
DB n
COUT
100pF
+2.1V
IOH
200µA
Figure 4. Load Circuit for Bus Timing Characteristics
REV. A
–3–
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