ADDC02808PBTV(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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ADDC02808PBTV Datasheet PDF : 20 Pages
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ADDC02808PB
8.1
Table II. Output Response to a 24 A (1 A-25 A) Step in
8
Load Current (Compensation Optimized)
7.9
Typical
Settling Time See
CLOAD
RESR
Deviation (Within 1%) Figure
7.8
1,000 µF 10 mΩ –4%
125 µs
23
7.7
2,000 µF 5 mΩ
–2.5%
100 µs
24
4,000 µF 2.5 mΩ –1%
0 µs
25
7.6
Connection to Load
7.5
Pulse performance is dependent on minimizing the parasitic im-
pedances in the connection between the converter output and
OBSOLETE 7.4
–200 –100 0 100 200 300 400 500 600 700 800
TIME – µs
Figure 21. Predicted Response for 24 A Step Load
Change in Load Current, di/dt = 12 A/µs, for CLOAD =
2,000 µF and RESR = 5 mΩ
8.1
8
7.9
7.8
7.7
7.6
7.5
the load and external capacitors. Low inductance and low resis-
tance connections should be used. Multilayer connections
should be avoided to minimize stray capacitance. The converter
should be placed as close to the load and external capacitors as
possible.
8.1
8
7.9
7.8
7.7
7.6
7.5
7.4
–200 –100 0 100 200 300 400 500 600 700 800
7.4
–200 –100 0 100 200 300 400 500 600 700 800
TIME – µs
TIME – µs
Figure 22. Predicted Response for 24 A Step Load
Change in Load Current, di/dt = 12 A/µs, for CLOAD =
4,000 µF and RESR = 2.5 mΩ
Factory Set Internal Compensation
If the user knows the external load capacitance and RESR to be
used in the application and if the application requires better
pulse response than is summarized in Table I, then the internal
feedback compensation can be modified at the factory to im-
prove the transient response. In these instances, the compensa-
tion is optimized for a particular CLOAD at the expense of
performing well over a broader range of CLOAD. The predicted
maximum output voltage deviation and settling times for fac-
tory-modified feedback compensation are shown in Figures 23,
24, and 25, and summarized in Table II, for three combinations
of CLOAD and RESR. As can be seen, optimizing the compensa-
tion for a given load capacitance gives the best transient re-
sponse in terms of both voltage deviation and settling time.
Figure 23. Predicted Response for 24 A Step Load Change,
di/dt = 12 A/µs, with Factory Set Internal Compensation
Optimized for CLOAD = 1,000 µF and RESR = 10 mΩ
8.1
8
7.9
7.8
7.7
7.6
7.5
7.4
–200 –100 0 100 200 300 400 500 600 700 800
TIME – µs
Figure 24. Predicted Response for 24 A Step Load Change,
di/dt = 12 A/µs, with Factory Set Internal Compensation
Optimized for CLOAD = 2,000 µF and RESR = 5 mΩ
REV. 0
–9–
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