HV7224 Ver la hoja de datos (PDF) - Supertex Inc
Número de pieza
componentes Descripción
Fabricante
HV7224 Datasheet PDF : 7 Pages
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Functional Block Diagram
VPP
OE
Polarity
VDD
DIOA
SHIFT
CLK
S/R
DIR
HV7224
P
LT
HVOUT1
N
LT
HVOUT 2
DIOB
GND
LT
LT = Level Translator
HVOUT 40
Function Table
I/O Relations
CLK
Inputs
DIR S/R Data
POL
OE
O/P HIGH
X
X
H
H
L
O/P OFF
X
X
L
X
L
O/P LOW
X
X
H
L
L
O/P OFF
X
X
X
X
H
Notes:
H = logic high level, L = logic low level, X = irrelevant
Data input (DRIO) loaded on the low-to-high transistion of the clock.
Only one active output can be set at a time.
Output Sequence Operation Table
DIR Shift Data Reset In Data Reset Out
L
L
H
L
L
H
H
H
DRIOB
DRIOA
DRIOB
DRIOA
DRIOA1
DRIOB2
DRIOA1
DRIOB2
HVOUT# Sequence
40 → 1
1 → 40
20 → 1 → 40 → 21
21 → 40 → 1 → 20
* Reference to package outline or chip layout drawing.
1.DRIOA is DRIOBdelayed by 40 clock pulses.
2. DRIOB is DRIOA delayed by 40 clock pulses.
HV Outputs
H
HIGH-Z
L
All O/P HIGH-Z
Direction*
Option (See pin-out on P. 12-158)
A
A
B
B
5
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