DC1826A-A Ver la hoja de datos (PDF) - Linear Technology

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DC1826A-A

18-Bit/16-Bit, 2.5Msps Low Noise, SAR ADCs with Pin-Configurable Analog Input Range

Linear Technology 

DEMO MANUAL DC1826A

DC1826A SETUP

Jumper and Switch Functions

JP1: Selects AC- or DC-coupling of AIN+. The default setting

is DC.

JP2: Selects AC- or DC-coupling of AIN–. The default setting

is DC.

JP3: VCM sets the DC bias for AIN+ and AIN– when the

inputs are AC-coupled. VREF /2 is the default setting.

JP4: VCCIO sets the output levels at J2 to either 3.3V

or 2.5V. Use 3.3V to interface to the DC718 which is the

default setting.

JP5: EEPROM default position is WP. The position of this

jumper should not be changed.

SW1

SER_PARL: Off enables serial operation. Sample rate is

the CLKIN frequency divided by 50. On enables parallel

operation. Sample rate is equal to the CLKIN frequency.

OB/2CL: Off enables offset binary output code in fully-

differential mode and unipolar range with straight binary

code in pseudo-differential mode. On enables 2’s comple-

ment output code in fully-differential mode and bipolar

range with 2’s complement output code in pseudo-dif-

ferential mode.

CSL: Off disables SDO and gates SCK off. On enables SDO

and gates SCK on.

PD/FDL: Off enables pseudo-differential mode. On enables

fully-differential mode.

The default position for all switches is on.

Figure 7. PScope Screenshot

dc1826afa

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