DC1826A-E Ver la hoja de datos (PDF) - Linear Technology

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DC1826A-E

18-Bit/16-Bit, 2.5Msps Low Noise, SAR ADCs with Pin-Configurable Analog Input Range

Linear Technology 

DEMO MANUAL DC1826A

DC1826A ASSEMBLY OPTIONS

ASSEMBLY VERSION

DC1826A-A

DC1826A-E

U1 PART NUMBER

LTC2389CMS-18

LTC2389CMS-16

MAX CONVERSION RATE

2.5Msps

2.5Msps

NUMBER OF BITS

18

16

SERIAL MAX CLKIN FREQUENCY

100MHz

100MHz

DC718 QUICK START PROCEDURE

Check to ensure that all switches and jumpers are set as

shown in the connection diagram of Figure 1. The default

connections configure the ADC to use the onboard refer-

ence and regulators to generate the required common

mode voltages. The analog input is DC-coupled. Connect

the DC1826A to a DC718 USB high speed data collection

board using connector J4. Then, connect the DC718 to

a host PC with a standard USB A/B cable. Apply ±9V to

the indicated terminals. Then, apply a low jitter signal

source to J2. The default setup uses a single-ended to

differential converter so that it is only necessary to apply

a single-ended input signal to J2. Connect a low jitter

2.5MHz (100MHz for serial) 3.3VP-P sine wave or square

wave to connector J1 for parallel operation. Note that J1

has a 49.9Ω termination resistor to ground.

Run the QuikEval II software (PScope.exe version K73 or

later) supplied with the DC718 or download it from www.

linear.com.

Complete software documentation is available from the

help menu. Updates can be downloaded from the tools

menu. Check for updates periodically as new features

may be added.

The PScope™ software should recognize the DC1826A

and configure itself automatically.

Click the collect button (see Figure 7) to begin acquiring

data. The collect button then changes to pause, which can

be clicked to stop data acquisition.

DC1826A SETUP

DC Power

The DC1826A requires ±9VDC and draws 100mA. Most

of the supply current is consumed by the CPLD, opamps,

regulators and discrete logic on the board. The 9VDC in-

put voltage powers the ADC through LT1763 regulators

which provide protection against accidental reverse bias.

Additional regulators provide power for the CPLD and

opamps. See Figure 1 for connection details.

Clock Source

You must provide a low jitter 3.3VP-P sine or square

wave to J1. The clock input is AC-coupled so the DC

level of the clock signal is not important. A generator

like the HP8644 or the DC1216A-A is recommended.

Even a good generator can start to produce noticeable

jitter at low frequencies. Therefore, it is recommended

for lower clock rates to divide down a higher frequency

clock to the desired sample rate. For serial operation, the

ratio of clock frequency to conversion rate is 50:1. The

maximum serial conversion rate is 2Msps. If the clock

input is to be driven with logic, it is recommended that

2

dc1826afa

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