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M2S56D20AKT Ver la hoja de datos (PDF) - Elpida Memory, Inc

Número de pieza
componentes Descripción
Fabricante
M2S56D20AKT
Elpida
Elpida Memory, Inc Elpida
M2S56D20AKT Datasheet PDF : 41 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
DDR SDRAM
E0338M10 (Ver.1.0)
(Previous Rev.1.54E)
Jan. '03 CP(K)
M2S56D20/ 30/ 40ATP
M2S56D20/ 30/ 40AKT
256M Double Data Rate Synchronous DRAM
AC TIMING REQUIREMENTS (1/2)
(TA=0 to 70oC, VDD = VDDQ = 2.5V +0.2V, VSS = VSSQ = 0V, unless otherwise noted)
Symbol
AC Characteristics Parameter
tAC DQ Output Valid data delay time from CLK//CLK
-60
Min.
Max
-0.70 0.70
-75A
Min.
Max
-0.75 0.75
-75
Unit Notes
Min.
Max
-0.75 0.75 ns
tDQSCK DQ Output Valid data delay time from CLK//CLK
-0.60 0.60
-0.75
0.75
-0.75 0.75 ns
tCH CLK High level width
0.45
0.55
0.45
0.55
0.45
0.55 tCK
tCL CLK Low level width
0.45
0.55
0.45
0.55
0.45
0.55 tCK
tCK CLK cycle time
CL=2.5
6
15
7.5
15
7.5
15
ns
CL=2
7.5
15
7.5
15
10
15
ns
tDS Input Setup time (DQ,DM)
0.45
0.5
0.5
ns 26,27
tDH Input Hold time(DQ,DM)
0.45
0.5
0.5
ns 26,27
tDIPW DQ and DM input pulse width (for each input)
1.75
1.75
1.75
ns
tHZ Data-out-high impedance time from CLK//CLK
-0.70 0.70
-0.75
0.75
-0.75 0.75 ns
14
tLZ Data-out-low impedance time from CLK//CLK
-0.70 0.70
-0.75
0.75
-0.75 0.75 ns
14
tDQSQ DQ Valid data delay time from DQS
tHP Clock half period
0.45
0.5
0.5
ns
tCLmin
tCLmin
tCLmin
or
or
or
ns
tCHmin
tCHmin
tCHmin
tQH Output DQS valid window
tHP-
tQHS
tHP-
tQHS
tHP-
tQHS
ns
tQHS Data Hold Skew Factor
tDQSS Write command to first DQS latching transition
tDQSH DQS input High level width
tDQSL DQS input Low level width
tDSS DQS falling edge to CLK setup time
tDSH DQS falling edge hold time from CLK
tMRD Mode Register Set command cycle time
tWPRES Write preamble setup time
tWPST Write postamble
tWPRE Write preamble
tIH Address and Control input hold time(fast slew rate)
tIS Address and Control input hold time(fast slew rate)
tIH Address and Control input hold time(Slow slew rate)
tIS Address and Control input hold time(Slow slew rate)
tRPST Read postamble
tRPRE Read preamble
0.55
0.75
0.75 tCK
0.75
1.25
0.75
1.25
0.75
1.25 tCK
0.35
0.35
0.35
tCK
0.35
0.35
0.35
tCK
0.2
0.2
0.2
tCK
0.2
0.2
0.2
tCK
12
15
15
ns
0
0
0
ns
16
0.4
0.6
0.4
0.6
0.4
0.6 tCK
15
0.25
0.25
0.25
tCK
0.75
0.9
0.9
ns 23,25
0.75
0.9
0.9
ns 23,25
0.8
0.9
0.9
ns 24,25
0.8
0.9
0.9
ns 24,25
0.4
0.6
0.4
0.6
0.4
0.6 tCK
0.9
1.1
0.9
1.1
0.9
1.1 tCK
20

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