M2S56D20AKT Ver la hoja de datos (PDF) - Elpida Memory, Inc
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M2S56D20AKT Datasheet PDF : 41 Pages
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DDR SDRAM
E0338M10 (Ver.1.0)
(Previous Rev.1.54E)
Jan. '03 CP(K)
M2S56D20/ 30/ 40ATP
M2S56D20/ 30/ 40AKT
256M Double Data Rate Synchronous DRAM
AC TIMING REQUIREMENTS (2/2)
(TA=0 to 70oC, VDD = VDDQ = 2.5V +0.2V, VSS = VSSQ = 0V, unless otherwise noted)
Symbol
AC Characteristics Parameter
tRAS Row Active time
tRC Row Cycle time(operation)
tRFC Auto Ref. to Active/Auto Ref. command period
tRCD Row to Column Delay
tRP Row Precharge time
tRRD Act to Act Delay time
tWR Write Recovery time
tDAL Auto Precharge write recovery + precharge time
tWTR Internal Write to Read Command Delay
tXSNR Exit Self Ref. to non-Read command
tXSRD Exit Self Ref. to -Read command
tXPNR Exit Power down to command
tXPRD Exit Power down to -Read command
tREFI Average Periodic Refresh interval
-60
Min.
Max
42 120,000
60
72
18
18
12
15
35
1
75
200
1
1
7.8
-75A
Min.
Max
45 120,000
65
75
20
20
15
15
35
1
75
200
1
1
7.8
-75
Min.
Max
45 120,000
65
75
20
20
15
15
35
1
75
200
1
1
7.8
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
tCK
tCK
tCK 18
us
17
Output Load Condition
VOUT
V TT =VREF
50Ω
Zo=50Ω
30pF
VREF
DQS
DQ
Output Timing
Measurement
Reference Point
VREF
VREF
CAPACITANCE
(TA=0 to 70oC, VDD = VDDQ = 2.5V + 0.2V, VSS = VSSQ = 0V, unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O
Parameter
Test Condition
Limits
Min. Max.
Delta
Cap.(Max.)
Unit
Input Capacitance, address pin
VI=1.25v 2.0 3.0
pF
0.50
Input Capacitance, control pin
f=100MHz 2.0 3.0
pF
Input Capacitance, CLK pin
VI=25mVrms 2.0 3.0
0.25
pF
I/O Capacitance, I/O, DQS, DM pin
4.0 5.0 0.50 pF
Notes
11
11
11
11
21
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