GS8322Z18B-133IV Ver la hoja de datos (PDF) - Giga Semiconductor

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Fabricante

GS8322Z18B-133IV

36Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

GS8322Z18/36/72(B/E/C)-xxxV

GS8322Z18/36E-xxxV 165-Bump BGA Pin Description

Symbol

A0, A1

An

A18

DQA

DQB

DQC

DQD

BA, BB, BC, BD

NC

CK

CKE

W

E1

E3

E2

FT

G

ADV

ZQ

ZZ

LBO

TMS

TDI

TDO

TCK

MCH

VDD

VSS

VDDQ

Type

I

I

I

I/O

I

—

I

I

I

I

I

I

I

I

I

I

I

I

I

I

O

I

—

I

I

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Address Input

Data Input and Output pins

Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

No Connect

Clock Input Signal; active high

Clock Enable; active low

Write Enable; active low

Chip Enable; active low

Chip Enable; active low

Chip Enable; active high

Flow Through / Pipeline Mode Control

Output Enable; active low

Burst address counter advance enable; active high

FLXDrive Output Impedance Control

Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

Sleep mode control; active high

Linear Burst Order mode; active low

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Must Connect High

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.05 6/2006

10/39

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2002, GSI Technology

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