ADP3302 Ver la hoja de datos (PDF) - Analog Devices
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ADP3302 Datasheet PDF : 8 Pages
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ADP3302
2.5V → 4.2V
C1
R1
100kΩ
R4
120kΩ
100µF
10V
AVX-TPS
ILIM VIN
R3
1MΩ
R2
90kΩ
SET
SW1
ADP3000
AO
FB
GND SW2
R5
330kΩ
R6
100kΩ
C2
33nF
Q1
2N2907
R8
10kΩ
R7
90kΩ
(SUMIDA–CDRH62)
L1
6.6µF
IN5817
R9
348kΩ
1%
R10
200kΩ
1%
C3
100µF
10V
AVX-TPS
IN
VO2
IN
ADP3302
SD GND VO2
1µF
6V C4
(MLC)
3V
100mA
1µF
6V C5
(MLC)
3V
100mA
Figure 20. Cell Li-Ion to 3 V/200 mA Converter with Shutdown at VIN < 2.5 V
OBSOLETE Phase One: When the input voltage is equal to 3.7 V or higher,
the ADP3000 is off and the ADP3302 operates on its own to
regulate the output voltage. At this phase, current is flowing into
the input pins of the ADP3302 via the inductor L1 and the
Schottky diode. At the same time, the ADP3000 is set into sleep
mode by pulling the FB pin (via R9 and R10 resistor divider
network) to about 10% higher than its internal reference which
is set to be 1.245 V.
Phase Two: As the input voltage drops below 3.7 V, the
decreasing input voltage causes the voltage of the FB pin to be
within 5% of the 1.245 V reference. This triggers the ADP3000
to turn on, providing a 3.4 V regulated output to the inputs of
the ADP3302. The ADP3000 continues to supply the 3.4 V
regulated voltage to the ADP3302 until the input voltage drops
below 2.5 V.
Phase Three: When the input voltage drops below 2.5 V, the
ADP3302 will shut down and the ADP3000 will go into sleep
Supply Sequencing Circuit
Figure 22 shows a simple and effective way to achieve sequenc-
ing of two different output voltages, 3.3 V and 5 V, in a mixed
supply voltage system. In most cases, these systems need careful
sequencing for the supplies to avoid latchup.
At turn-on, D1 rapidly charges up C1 and enables the 5 V out-
put. After a R2-C2 time constant delay, the 3.3 V output is
enabled. At turn-off, D2 quickly discharges C2 and R3 pulls
SD1 low, turning off the 3.3 V output first. After a R1-C1 time
constant delay, the 5 V output turns off.
VIN = 6V TO 12V
C5
1µF
D2
3.3V
ON/OFF
C2
0.01µF
D1
D3
R3
330kΩ
2
8 IN ERR
5 IN
OUT1 1
7 SD1
ADP3302
OUT2 4
6 SD2
C3
0.5µF
VOUT1
3.3V
VOUT2
C4
5.0V
mode. With the input voltage below 2.5 V, the resistor divider
network, R1 and R2, applies a voltage that is lower than the
ADP3000’s internal 1.245 V reference voltage to the SET pin.
C1
0.01µF
R1
220kΩ
R2
220kΩ
GND
3
0.5µF
This causes the AO pin to have a voltage close to 0 V, which
causes the ADP3302 to go into shutdown directly and Q1 to
turn on and pull the FB pin 10% or higher than the internal
1.245 V reference voltage. With the FB pin pulled high, the
Figure 22. Turn-On/Turn-Off Sequencing for Mixed Supply
Voltages
ADP3000 goes into sleep mode.
80
AT VIN ≤ 2.5V
SHDN IQ = 500µA
IO = 50mA + 50mA
75
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin SOIC
(SO-8)
70
IO = 100mA + 100mA
0.1968 (5.00)
0.1890 (4.80)
65
VIN
2.6
3.0
3.4
3.8
4.2
(V)
8
0.1574 (4.00)
0.1497 (3.80) 1
5
0.2440 (6.20)
4 0.2284 (5.80)
Figure 21. Typical Efficiency of the Circuit of Figure 20
Refer to Figure 20. R9 and R10 set the output voltage of the
ADP3000. R1, R2, and R3 set the shutdown threshold voltage
for the circuit. For further details on the ADP3000, please refer
to the ADP3000 data sheet.
PIN 1
0.0098 (0.25)
0.0040 (0.10)
0.0688 (1.75)
0.0532 (1.35)
0.0196
0.0099
(0.50)
(0.25)
x
45°
SEATING
PLANE
0.0500 0.0192 (0.49)
(1.27) 0.0138 (0.35)
BSC
0.0098 (0.25)
0.0075 (0.19)
8°
0° 0.0500 (1.27)
0.0160 (0.41)
–8–
REV. 0
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