M80C286 Ver la hoja de datos (PDF) - Intel

Número de pieza

componentes Descripción

Fabricante

M80C286

HIGH PERFORMANCE CHMOS MICROPROCESSOR WITH MEMORY MANAGEMENT AND PROTECTION

Intel 

M80C286

271103 – 28

NOTES

1 Data is ignored upper data bus D8 – D15 should not change state during this time

2 First INTA cycle should have at least one wait state inserted to meet M8259A minimum INTA pulse width

3 Second INTA cycle should have at least one wait state inserted to meet M8259A minimum INTA pulse width

4 LOCK is active for the first INTA cycle to prevent a bus arbiter from releasing the bus between INTA cycles in a multi-

master system LOCK is also active for the second INTA cycle

5 A23 – A0 exits 3-state OFF during w2 of the second TC in the INTA cycle See section on bus hold circuitry

6 Upper data bus should not change state during this time

Figure 30 Interrupt Acknowledge Sequence

Halt or Shutdown Cycles

The M80C286 externally indicates halt or shutdown

conditions as a bus operation These conditions oc-

cur due to a HLT instruction or multiple protection

exceptions while attempting to execute one instruc-

tion A halt or shutdown bus operation is signalled

when S1 S0 and COD INTA are LOW and M IO is

HIGH A1 HIGH indicates halt and A1 LOW indi-

cates shutdown The 82288 bus controller does not

issue ALE nor is READY required to terminate a halt

or shutdown bus operation

During halt or shutdown the M80C286 may service

PEREQ or HOLD requests A processor extension

segment overrun exception during shutdown will in-

hibit further service of PEREQ Either NMI or RESET

will force the M80C286 out of either halt or shut-

down An INTR if interrupts are enabled or a proc-

essor extension segment overrun exception will also

force the M80C286 out of halt

30

Share Link: