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M80C286

HIGH PERFORMANCE CHMOS MICROPROCESSOR WITH MEMORY MANAGEMENT AND PROTECTION

Intel 

M80C286

Processor Extension Transfers

The processor extension interface uses I O port ad-

dresses 00F8(H) 00FA(H) and 00FC(H) which are

part of the I O port address range reserved by Intel

An ESC instruction with Machine Status Word bits

EM e 0 and TS e 0 will perform I O bus operations

to one or more of these I O port addresses indepen-

dent of the value of IOPL and CPL

ESC instructions with memory references enable the

CPU to accept PEREQ inputs for processor exten-

sion operand transfers The CPU will determine the

operand starting address and read write status of

the instruction For each operand transfer two or

three bus operations are performed one word trans-

fer with I O port address 00FA(H) and one or two

bus operations with memory Three bus operations

are required for each word operand aligned on an

odd byte address

NOTE

Odd-aligned numerics instructions should be avoid-

ed when using an M80C286 system running six or

more memory-write wait-states The M80C286 can

generate an incorrect numerics address if all the

following conditions are met

Two floating point (FP) instructions are fetched

and in the M80C286 queue

The first FP instruction is any floating point store

except FSTSW AX

The second FP instruction is any floating point

store except FSTSW AX

The second FP instruction accesses memory

The operand of the first instruction is aligned on

an odd memory address

More than five wait-states are inserted during ei-

ther of the last two memory write transfers

(transferred as two bytes for odd aligned oper-

ands) of the first instruction

The second FP instruction operand address will be

incremented by one if these conditions are met

These conditions are most likely to occur in a multi-

master system For a hardware solution contact

your local Intel representative

Ten or more command delays should not be used

when accessing the numerics coprocessor Exces-

sive command delays can cause the M80C286 and

M80C287 to lose synchronization

Interrupt Acknowledge Sequence

Figure 30 illustrates an interrupt acknowledge se-

quence performed by the M80C286 in response to

an INTR input An interrupt acknowledge sequence

consists of two INTA bus operations The first allows

a master M8259A Programmable Interrupt Control-

ler (PIC) to determine which if any of its slaves

should return the interrupt vector An eight bit vector

is read on D0 – D7 of the M80C286 during the sec-

ond INTA bus operation to select an interrupt han-

dler routine from the interrupt table

The Master Cascade Enable (MCE) signal of the

M82C288 is used to enable the cascade address

drivers during INTA bus operations (See Figure 30)

onto the local address bus for distribution to slave

interrupt controllers via the system address bus The

M80C286 emits the LOCK signal (active LOW) dur-

ing Ts of the first INTA bus operation A local bus

‘‘hold’’ request will not be honored until the end of

the second INTA bus operation

Three idle processor clocks are provided by the

M80C286 between INTA bus operations to allow for

the minimum INTA to INTA time and CAS (cascade

address) out delay of the M8259A The second INTA

bus operation must always have at least one extra

Tc state added via logic controlling READY This is

needed to meet the M8259A minimum INTA pulse

width

Local Bus Usage Priorities

The M80C286 local bus is shared among several

internal units and external HOLD requests In case

of simultaneous requests their relative priorities are

(Highest) Any transfers which assert LOCK either

explicitly (via the LOCK instruction prefix)

or implicitly (i e some segment descriptor

accesses interrupt acknowledge se-

quence or an XCHG with memory)

The second of the two byte bus opera-

tions required for an odd aligned word op-

erand

The second or third cycle of a processor

extension data transfer

Local bus request via HOLD input

Processor extension data operand trans-

fer via PEREQ input

Data transfer performed by EU as part of

an instruction

(Lowest) An instruction prefetch request from BU

The EU will inhibit prefetching two proc-

essor clocks in advance of any data

transfers to minimize waiting by EU for a

prefetch to finish

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