AD8116 Ver la hoja de datos (PDF) - Analog Devices
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AD8116 Datasheet PDF : 26 Pages
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AD8116
TIMING CHARACTERISTICS
Parameter
Symbol
Min
Data Setup Time
t1
20
CLK Pulsewidth
t2
100
Data Hold Time
t3
20
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulsewidth
t4
100
t5
0
t6
50
CLK to DATA OUT Valid
t7
Propagation Delay, UPDATE to Switch On or Off
–
Data Load Time, CLK = 5 MHz
–
CLK, UPDATE Rise and Fall Times
–
RESET Time
–
Limit
Typ
16
Max
200
50
100
200
Units
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
1
CLK
0
1
DATA IN
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
DATA OUT
t2
t1
t3
OUT15 (D4)
t7
t4
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
OUT15 (D3)
OUT00 (D0)
t5
t6
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
CLOCK
DATA IN
0 1 2 3 4 5 6 7 8 9 10
15
20
25
75
79
UPDATE
T=0
INCREASING TIME
Figure 2. Timing Diagram and Programming Example
VIH
CLK, DATA IN,
CE, UPDATE
2.0 V min
VIL
VOH
CLK, DATA IN, DATA OUT
CE, UPDATE
0.8 V max
2.7 V min
Table I. Logic Levels
VOL
DATA OUT
0.5 V max
IIH
IIL
IOH
CLK, DATA IN, CLK, DATA IN, DATA OUT
CE, UPDATE
CE, UPDATE
20 µA max
–400 µA min
–400 µA max
IOL
DATA OUT
3.0 mA min
REV. A
–3–
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