MR82510 Ver la hoja de datos (PDF) - Intel

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Fabricante

MR82510

ASYNCHRONOUS SERIAL CONTROLLER

Intel 

M82510

off the particular block interrupt request in GSR via

the General Enable Register Another method

which is applicable to all sources is to issue the

Status Clear command from the Internal Command

Register The detailed service requirements for each

source are given below

Table 5 Service Procedures

Interrupt Status Bits Interrupt

Source Registers Masking

Specific

Service

Timers TMST (1– 0) TMIE (1–0) Read TMST

GSR (5) GER (5)

Tx

GSR (4)

Machine LSR (6)

GER (4) Write Character

to tX FIFO

Rx

LSR (4– 1)

Machine RST (7– 1)

GSR (2)

RIE (7–1)

GER (2)

Read RST or

LSR Write 0

to bit in

RST LSR

Rx FIFO RST LSR (0) GER (0)

GSR (0)

Write 0 to

LSR RST

Bit zero

Read Character

Tx FIFO LSR (5)

GSR (1)

GER (1) Write to FIFO

Read GIR(1)

Modem MSR (3-0)

GSR (3)

MIE (3-0)

GER (3)

Read MSR

write 0 into the

appropriate bits

of MSR (3– 0)

NOTE

1 Only if pending interrupt is Tx FIFO

System Clock Generation

The M82510 has two modes of System Clock Oper-

ation It can accept an externally generated clock or

it can use a crystal to internally generate its system

clock

CRYSTAL OSCILLATOR

Parallel Resonant Crystal

271072 –5

Figure 5 Crystal Oscillator

The M82510 has an on-chip oscillator to generate its

system clock The oscillator will take the inputs from

a crystal attached to the X1 and X2 pins This mode

is configured via a hardware strapping option on

RTS

271072 – 6

Figure 6 Strapping Option

During hardware reset the RTS pin is an input it is

weakly pulled high from within and then checked If it

is driven low externally then the M82510 is config-

ured for the Crystal Oscillator otherwise an external

clock is expected

EXTERNALLY GENERATED SYSTEM CLOCK

271072 – 7

Figure 7 External Clock

This is the default configuration Under normal con-

ditions the system clock is divided by two however

the user may disable divide by two via a hardware

strapping option on the DTR pin The Hardware

strapping option is similar to the one used on the

RTS pin It is forbidden to strap both DTR and RTS

Transmit

The two major blocks involved in transmission are

the Transmit FIFO and the Transmit Machine The

Tx FIFO acts as a buffer between the CPU and the

Tx Machine Whenever a data character is written to

the Transmit Data register it along with the Trans-

mit Flags (if applicable) is loaded into the Tx FIFO

7

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