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AD1878

High Performance 16-/18-Bit ΣΔ Stereo ADCs

Analog Devices 

AD1878/AD1879

In the “slave modes,” the bit clock (BCK), the word clock

(WCK), and the left/right clock (LRCK) are user-supplied in-

puts. Note that, for performance reasons, the AD1878/AD1879

does not support asynchronous operation; these clocks must be

externally derived from the master clock (CLOCK). The func-

tional sequence of the signals in the slave modes is identical to

the master modes with word clock input, and they share the

same sequence timing diagrams.

In 64-Bit Master Mode with Word Clock Output, the 16-/18-bit

words are right-justified in 32-bit fields as shown in Figures 7

and 8. The WCK output goes HI approximately with the falling

edge of the BCK output, indicating that the MSB on DATA will

be externally valid at the next BCK rising edge. The LRCK out-

put discriminates the left from the right output fields.

In 64-bit frame modes with word clock (WCK) is an input, the

16-/18-bit words can be placed in user-defined locations within

32-bit fields. This is true in both master and slave modes. The

options are illustrated in Figures 9, 10, 11, and 12. For all op-

tions, the first occurrence in a 32-bit field when the word clock

(WCK) is HI on a bit clock (BCK) falling edge will cause the

beginning of data transmission. The MSB on DATA will be

valid at the next BCK rising edge. Again, the LRCK output dis-

criminates the left from the right output fields.

Figure 9 illustrates the general case for 64-bit frame modes with

word clock input where the MSB is valid on the rising edge of

the Nth bit clock (BCK). Figures 10 and 11 illustrate the limits.

If WCK is still LO at the falling edge of the 14th bit clock (BCK)

for the AD1879 or 16th bit clock (BCK) for the AD1878, then the

MSB of the current word will be output anyway, valid at the ris-

ing edge of the 15th bit clock (BCK) in the field for the AD1879,

17th for the AD1878. This limit insures that all 16/18 bits will

be output within the current field. The effect is to right-justify

the data.

32 1 2 3

BCK

OUTPUT

WCK

OUTPUT

LRCK

OUTPUT

PREVIOUS DATA

DATA LSB

OUTPUT

ZEROS

14 15 16 17 18

29 30 31 32 1 2 3

LEFT DATA

MSB MSB–1 MSB–2 MSB–3

LSB–3 LSB–2 LSB–1 LSB

ZEROS

14 15 16 17 18

29 30 31 32 1

RIGHT DATA

MSB MSB–1 MSB–2 MSB–3

LSB–3 LSB–2 LSB–1 LSB

Figure 7. AD1879 64-Bit Output Timing with WCK as Output (Master Mode Only)

BCK

OUTPUT

WCK

OUTPUT

32 1

23

LRCK

OUTPUT

PREVIOUS DATA

DATA

OUTPUT

LSB

ZEROS

14 15 16 17 18

29 30 31 32 1 2 3

LEFT DATA

MSB MSB–1 LSB–3 LSB–2 LSB–1 LSB

ZEROS

14 15 16 17 18

29 30 31 32 1

RIGHT DATA

MSB MSB–1 LSB–3 LSB–2 LSB–1 LSB

Figure 8. AD1878 64-Bit Frame Output Timing with WCK as Output (Master Mode Only)

BCK I/O

32 1

N–1 N N+1 N+14 N+15 N+16 N+17 31 32 1

N–1 N N+1 N+14 N+15 N+16 N+17 31 32 1

WCK INPUT

LRCK I/O

AD1879

DATA OUTPUT

AD1878

DATA OUTPUT

ZEROS

ZEROS

LEFT DATA

MSB MSB–1 LSB–3 LSB-2 LSB–1 LSB

LEFT DATA

MSB MSB–1 LSB–1 LSB

ZEROS

ZEROS

RIGHT DATA

MSB MSB–1

RIGHT DATA

MSB MSB–1

LSB–3 LSB-2 LSB–1 LSB

LSB–1 LSB

ZEROS

ZEROS

Figure 9. AD1878/AD1879 64-Bit Frame Output Timing with WCK as Input: WCK Transitions HI Before 16th BCK

(AD1878)/14th BCK (AD1879) (Master Mode or Slave Mode)

–10–

REV. 0

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