M27W202-120F6TR Ver la hoja de datos (PDF) - STMicroelectronics
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M27W202-120F6TR Datasheet PDF : 15 Pages
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M27W202
Figure 6. Programming and Verify Modes AC Waveforms
A0-A15
Q0-Q15
VPP
VCC
E
P
G
tAVPL
DATA IN
tQVPL
VALID
tPHQX
DATA OUT
tVPHPL
tGLQV
tVCHPL
tELPL
tPLPH
tQXGL
tGHQZ
tGHAX
PROGRAM
VERIFY
AI00706
Figure 7. Programming Flowchart
VCC = 6.25V, VPP = 12.75V
n =0
NO
++n
= 25
YES
P = 100µs Pulse
NO
VERIFY
YES
++ Addr
FAIL
Last NO
Addr
YES
CHECK ALL WORDS
1st: VCC = 5V
2nd: VCC = 2.7V
AI02734
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows pro-
gramming of the whole array with a guaranteed
margin, in a typical time of 13 seconds. Program-
ming with PRESTO II consists of applying a se-
quence of 100 µs program pulses to each word
until a correct verify occurs (see Figure 7). During
programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
enough margin. No overprogram pulse is applied
since the verify in MARGIN MODE at VCC much
higher than 3.6V, provides necessary margin to
each programmed cell.
Program Inhibit
Programming of multiple M27W202s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27W202 may be common. A TTL low level pulse
applied to a M27W202’s P input, with E low and
VPP at 12.75V, will program that M27W202. A high
level E input inhibits the other M27W202s from be-
ing programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
and G at VIL, P at VIH, VPP at 12.75V and VCC at
6.25V.
8/15
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