MC12439FN Ver la hoja de datos (PDF) - Motorola => Freescale

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componentes Descripción

Fabricante

MC12439FN

High Frequency Clock Generator

Motorola => Freescale 

MC12439

25

20

15

6.25ps Reference

10

5

0

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

Output Frequency (MHz)

Figure 8. RMS Jitter versus Output Frequency

NO TAG shows the jitter as a function of the output

frequency. For the 12439 this information is probably of more

importance. The flat line represents an RMS jitter value that

corresponds to an 8 sigma ±25ps peak–to–peak long term

period jitter. The graph shows that for output frequencies

from 87.5 to 400MHz the jitter falls within the ±25ps

peak–to–peak specification. The general trend is that as the

output frequency is decreased the output edge jitter will

increase.

The jitter data from NO TAG and NO TAG do not include

the performance of the 12439 when the output is in the divide

by 1 mode. In divide by one mode the output signal is a

digitally doubled version of the VCO output. The period of the

outputs of the digital doubler is dependent on the duty cycle

of the VCO output. Since the VCO output duty cycle cannot

be guaranteed to be always 50% the resulting 12439 output

in divide by one mode will be bimodal at times. Since a

bimodal distribution cannot be acurately represented with an

rms value, peak–to–peak values of jitter for the divide by one

mode are presented.

Figure 9 shows the peak–to–peak jitter of the 12439

output in divide by one mode as a function of output

frequency. Notice that as with the other modes the jitter

improves with increasing frequency. The ±65ps shown in the

data sheet table represents a conservative value of jitter,

especially for the higher vco, and thus output frequencies.

140

120

100

Spec Limit

N=1

80

60

40

400

500

600

700

800

Output Frequency (MHz)

Figure 9. Peak–to–Peak Jitter versus

Output Frequency

The jitter data presented should provide users with

enough information to determine the effect on their overall

timing budget. The jitter performance meets the needs of

most system designs while adding the flexibility of frequency

margining and field upgrades. These features are not

available with a fixed frequency SAW oscillator.

Output Voltage Swing vs Frequency

In the divide by one mode the output rise and fall times will

limit the peak to peak output voltage swing. For a 400MHz

output the peak to peak swing of the 12439 output will be

approximately 700mV. This swing will gradually degrade as

the output frequency increases, at 800MHz the output swing

will be reduced to approximately 500mV. For a worst case

analysis it would be safe to assume that the 12439 output will

always generate at least a 400mV output swing. Note that

most high speed ECL receivers require only a few hundred

millivolt input swings for reliable operation. As a result the

output generated by the 12439 will, under all conditions, be

sufficient for clocking standard ECL devices. Note that if a

larger swing is desired the 12439 could drive a single gate

ECLinPS Lite amplifier like the MC100LVEL16. The LVEL16

will speed up the output edge rates and produce a full swing

ECL output at 800MHz.

TIMING SOLUTIONS

9

BR1333 — Rev 6

MOTOROLA

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