MX29F1615 Ver la hoja de datos (PDF) - Macronix International
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MX29F1615 Datasheet PDF : 26 Pages
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DATA PROTECTION
The MX29F1615 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transitions. During power up the device automatically
resets the internal state machine in the Read Array mode.
Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion
of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up and
power-down, a write cycle is locked out for VCC less than
VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the
command register is disabled and all internal program/
erase circuits are disabled. Under this condition the device
will reset to the read mode. Subsequent writes will be
ignored until the VCC level is greater than VLKO. It is the
user's responsibility to ensure that the control pins are
logically correct to prevent unintentional write when VCC is
above VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 10ns (typical) on CE will not
initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL,CE =
VIH or BYTE/VPP=VIH/VIL To initiate a write cycle CE
must be a logical zero, BYTE/VPP must be at VHH while
OE is a logical one.
MX29F1615
P/N: PM0615
REV. 1.1, JUN. 15, 2001
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