HM-65262/883 Ver la hoja de datos (PDF) - Intersil
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HM-65262/883 Datasheet PDF : 10 Pages
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HM-65262/883
Intersil CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are guaran-
teed over temperature. The following rules ensure data
retention:
1. Chip Enable (E) must be held high during data retention;
within VCC to VCC +0.3V.
2. On RAMs which have selects or output enables (e.g., S,
G), one of the selects or output enables should be held in
the deselected state to keep the RAM outputs high
impedance, minimizing power dissipation.
3. Inputs which are to be held high (e.g., E) must be kept
between VCC +0.3V and 70% of VCC during the power
up and down transitions.
4. The RAM can begin operation >55ns after VCC reaches
the minimum operating voltage (4.5V).
VCC
E
Test Circuit
4.5V
DATA RETENTION
MODE
VCC ≥ 2.0V
VCC -0.3V TO VCC +0.3V
4.5V
>55ns
FIGURE 5. DATA RETENTION TIMING
DUT
(NOTE 1) CL
IOH
+
-
1.5V
IOL
NOTE:
1. Test head capacitance includes stray and jig capacitance.
EQUIVALENT CIRCUIT
211
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