CXA1690Q Ver la hoja de datos (PDF) - Sony Semiconductor

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CXA1690Q

Head Amplifier for Digital CCD Cameras

Sony Semiconductor 

Description of Operation

1. Camera signal processing system

Process the video signal processing pins as follows only in camera mode.

<5> VSHP ... Connect to GND.

<29> LINE ... Connect to GND via the capacitor (approx. 0.01µF).

<31> RFCONT ... Connect to GND.

<32> PBRFC ... Connect to GND via the capacitor (approx. 0.01µF).

Operating conditions

The camera signal processing system operates when CAM/VIDEO is High, and PB/REC is Low.

Camera Signal Processing System Timing Chart

CCD output

Signal

interval

Precharge level

OPB

interval

Dummy pixel

interval

Signal

interval

CXA1690Q

SHP

SHD

SH1 output

SH2 output

SH3 output

CLPDM

(Dummy bit section 2µ

for the dummy pixel interval)

AGC output

–N

times

(

SH3 output

– SH2 output

)

XRS

CLPOB

(2µ for the OPB interval)

CAMSH output

PBLK

(10µ for the dummy

pixel interval)

BLK output

CAMVISW output

DRVOUT output

CLPDM

CLPOUT output

Signal level

2.6V

[∗1]

[∗2]

2.6V

Basic black level

2.05V

[∗3]

2µs

Black level

2µs

2.05V

10µs

[∗4]

2.05V – Vf ≈ 1.25V

2µs

– 12 –

[∗5]

Approx. 2.1V when OFFSET is 0V

Approx. 2.0V for

20

50

VCC

Approx. 2.5V for

50

50

VCC

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