XE1209 Ver la hoja de datos (PDF) - Semtech Corporation
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XE1209 Datasheet PDF : 10 Pages
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XE1209
Ultra Low Power CMOS Transceiver
6.2 RECEIVE MODE
The data available at receiver output are valid between 20% and 60% of the data period (1/DR) after the rising edge
of the clock (DCLK) as shown in figure below. The received data rate must be 1820 bit/s +/- 2 % for proper bit
synchronizer operation. In addition, the bit synchronizer needs to see at least one transition (from “1” to “0” or from
“0” to “1”) every 8 bits present at its input.
60% of 1/DR
20% of 1/DR
1/DR
DATA
DCLK
At the beginning of the reception, the bit synchronizer needs to receive a preamble which is a sequence of 16 “0”
and “1” bit sent alternatively.
6.3 CARRIER DETECTION MODE
The Carrier Detection mode is active when the TR bit in the configuration register is 0 and the RE input pin is 1. The
signal present at RF inputs is amplified and compared to a voltage threshold. When a RF signal is present at the
input, the comparator output is a square wave at a frequency equal to the frequency of the RF signal. This signal is
fed into a 3-bit counter, whose output is directly available on the DATA pin. In this case, the DATA signal is a square
wave whose frequency is 1/8 of the RF carrier frequency.
RE
(TR=0)
RFIN
(shown as
square wave)
DATA
~ 4.8 ms
The carrier detector set-up time (after TR bit set to 0 and RE input set to 1) is 4.85ms when the carrier frequency is
36.86 kHz. In the applications where the carrier detector is turned on for a relative long period (tens to hundreds of
ms), it is recommended to reset the block with a short transition to stand-by mode (RE=0).
The timing diagram of the carrier detection is shown below when a RF signal is present at input and the function is
programmed.
© Semtech 2005
www.semtech.com
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