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T7121-EL2

HDLC Interface for ISDN (HIFI-64)

Agere -> LSI Corporation 

Data Sheet

April 1997

T7121 HDLC Interface for ISDN (HIFI-64)

Features

Description

s Low-cost device for B-channel (64 kbits/s) or

D-channel (16 kbits/s) data transport.

s Optional transparent mode—no HDLC framing is

performed.

s Frame sync (FS) allows a slot-select feature to

access an individual time slot in any TDM data

stream (e.g., Lucent Technologies Microelectronics

Group Concentration Highway Interface [CHI] or

subset).

s Bit-masking option allows effective data rates of 8,

16, 24, 32, 40, 48, and 56 kbits/s.

s Maximum data rate up to 4.096 MHz.

s Serial data-transfer pins for direct connection to the

Lucent ISDN line transceiver T7250C.

s Supports IOM2, K2, GCI, and SLD interface.

s Parallel microprocessor interface with either multi-

plexed or demultiplexed address and data lines for

easy interface with any microprocessor.

s Single interrupt output signal with seven maskable

interrupt conditions.

s Programmable interrupt modes.

s Memory-mapped read and write registers.

s TTL/CMOS compatible input/output.

s 3-state output pins to assist system diagnostics.

s Low-power 1.25 µm CMOS:

— 30 mW typical operation at 12 MHz.

— 5 mW standby mode (typical).

s HDLC transceiver:

— Stand-alone HDLC framing operation.

— 64-byte FIFO in both transmit and receive direc-

tions.

— Supports block-move instruction.

— Multiple frames allowed in FIFO.

— Programmable FIFO full- and empty-level inter-

rupt.

The T7121 HDLC Interface for ISDN (HIFI-64) con-

nects serial communications links carrying HDLC bit-

synchronous data frames to 8-bit microcomputer sys-

tems. There is an optional transparent mode of oper-

ation in which no HDLC processing is performed on

user data. The device communicates with the system

microprocessor as a memory-mapped peripheral and

is controlled by reading and writing 19 internal regis-

ters. The chip can be instructed to interrupt the

microprocessor when it detects certain events requir-

ing microprocessor attention. The HDLC transmitter

and receiver are each buffered with 64-byte, first-in-

first-out (FIFO) memory storage. The 64-byte buffer

depth reduces the number of status polls or inter-

rupts to be processed by the microprocessor, improv-

ing overall system efficiency. The major blocks are

the microprocessor interface, transmit and receive

FIFO memory buffers, HDLC processor, and a con-

centration highway interface (see Figure 1). The

T7121 device is available in a 28-pin, plastic DIP or a

28-pin, plastic, small-outline, J-lead (SOJ) package

for surface mounting.

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