UR5596(2005) Ver la hoja de datos (PDF) - Unisonic Technologies

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componentes Descripción

Fabricante

UR5596
(Rev.:2005)

DDR TERMINATION REGULATOR

Unisonic Technologies 

UR5596

MOS IC

FOR DDR-II APPLICATIONS

As a result of the separate VDDQ pin and an internal resistor divider, UR5596 can be utilized in DDR-II system,

figure 5 and 6 show two recommended circuits in DDR-II SDRAM application. The output stage is connected to the

1.8V rail and the AVIN pin can be connected to either a 3.3V or 5V rail. If it is not desirable to use the 1.8V rail it is

possible to connect the output stage to a 3.3V rail. The power dissipation increasing concern must be careful as well

SSTL-II application. The advantage of configuration of figure 6 is that it has the ability to source and sink a higher

maximum continuous current.

SHDN

VDDQ=1.8V

AVIN=2.2V ～ 5.5V

PVIN=1.8V

+

CIN

UTC UR5596

SHDN

VDDQ

AVIN

VREF

VSENSE

PVIN

VTT

GND

+

CREF

VREF=0.9V

+

COUT

VTT=0.9V

Figure 5. Recommended DDR-II Termination

SHDN

VDDQ=1.8V

AVIN=3.3V or 5.5V

PVIN=3.3V

+

CIN

UTC UR5596

SHDN

VDDQ

AVIN

VREF

VSENSE

PVIN

VTT

GND

+

CREF

VREF=0.9V

+

COUT

VTT=0.9V

Figure 6. DDR-II Termination with higher voltage rails

UNISONIC TECHNOLOGIES CO., LTD

www.unisonic.com.tw

8

QW-R502-045,A

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