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TE28F800C3BA90

Intel Advanced+ Boot Block Flash Memory (C3)

Intel 

Intel£ Advanced+ Boot Block Flash Memory (C3)

3.1.4

3.1.5

Standby

Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby

mode, which substantially reduces device power consumption without any latency for subsequent

read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If

deselected during a Program or Erase operation, the device continues to consume active power

until the Program or Erase operation is complete.

Reset

From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a high-

impedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required

until the initial read-access outputs are valid. A delay (tPHWL or tPHEL) is required after return from

reset before a write cycle can be initiated. After this wake-up interval, normal operation is restored.

The CUI resets to read-array mode, the status register is set to 0x80, and all blocks are locked. See

Figure 10, “Reset Operations Waveforms” on page 48.

If RP# is taken low for time tPLPH during a Program or Erase operation, the operation will be

aborted and the memory contents at the aborted location (for a program) or block (for an erase) are

no longer valid, since the data may be partially erased or written. The abort process goes through

the following sequence:

1. When RP# goes low, the device shuts down the operation in progress, a process which takes time

tPLRH to complete.

2. After time tPLRH, the part will either reset to read-array mode (if RP# is asserted during tPLRH) or

enter reset mode (if RP# is deasserted after tPLRH). See Figure 10, “Reset Operations Waveforms”

on page 48.

In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/tPHEL

must be observed before a Read or Write operation is initiated, as discussed in the previous

paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when

RP# goes high.

As with any automated device, it is important to assert RP# during a system reset. When the system

comes out of reset, the processor expects to read from the flash memory. Automated flash

memories provide status information when read during program or Block-Erase operations. If a

CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the

flash memory may be providing status information instead of array data. Intel® Flash memories

allow proper CPU initialization following a system reset through the use of the RP# input. In this

application, RP# is controlled by the same RESET# signal that resets the system CPU.

18

Datasheet

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