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M-TDAT162G52-3BAL2

MARS®2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface

Agere -> LSI Corporation 

Data Sheet

August 18, 2004

MARS2G5 P-Pro (TDAT162G52) SONET/SDH

155/622/2488 Mbits/s Data Interface

Table of Contents (continued)

Contents

Page

PP Register Map ............................................................................................................................................ 317

Path Terminator (PT)............................................................................................................................................ 345

Introduction .................................................................................................................................................... 345

SPE Mapper................................................................................................................................................... 346

Supported SPE Formats ................................................................................................................................ 349

SPE Mapper Architecture............................................................................................................................... 352

Transpose Block ............................................................................................................................................ 356

PT Register Descriptions ............................................................................................................................... 357

PT Register Map (Entire PT Except RXT Block)............................................................................................ 385

STS Receive Terminator (RXT) Block.................................................................................................................. 391

Introduction .................................................................................................................................................... 391

Receive Timing Functions.............................................................................................................................. 393

Pointer Interpreter Functions.......................................................................................................................... 394

Concatenation ................................................................................................................................................ 398

RXT Register Descriptions............................................................................................................................. 414

RXT Register Map.......................................................................................................................................... 460

DS3/E3 Block ....................................................................................................................................................... 486

DS3 Functional Description............................................................................................................................ 486

DS3 Transmit Direction .................................................................................................................................. 494

FIFO Block ..................................................................................................................................................... 494

DS3 PLCP Frame/Data Insert........................................................................................................................ 495

DS3 Frame Generate/OH Bit Inserter ............................................................................................................ 497

Transparent Payload Mode (Used in Conjunction with DS3 Mapping) .......................................................... 498

E3 Functional Description .............................................................................................................................. 499

DS3 Register Descriptions ............................................................................................................................. 518

E3 Register Descriptions................................................................................................................................ 550

DS3 Register Map.......................................................................................................................................... 582

E3 Register Map ............................................................................................................................................ 595

Appendix: DS3 to STS-1 Mapping ................................................................................................................. 609

Receive Sequencer (RXS) Block.......................................................................................................................... 611

Introduction .................................................................................................................................................... 611

RXS PRBS Monitor ........................................................................................................................................ 612

RXS Register Descriptions............................................................................................................................. 613

RXS Register Maps........................................................................................................................................ 618

Data Engine Block ................................................................................................................................................ 623

Data Engine Block—Subblocks ..................................................................................................................... 623

Data Engine Block—ATM Framer/Frame Inserter Subblock................................................................................ 624

Overview ........................................................................................................................................................ 624

Capabilities..................................................................................................................................................... 624

Architecture .................................................................................................................................................... 626

Data Engine Block—HDLC Framer and Escaper Subblock ................................................................................. 627

Introduction .................................................................................................................................................... 627

Features ......................................................................................................................................................... 627

Byte-Synchronous Mode................................................................................................................................ 628

Examples of Byte-Synchronous Mode Escaper Operation ............................................................................ 629

Examples of Byte-Synchronous Mode Framer Operation.............................................................................. 631

Bit-Synchronous Mode................................................................................................................................... 632

Examples of Bit-Synchronous Mode Framer Operation................................................................................. 634

Examples of Bit-Synchronous Mode Escaper Operation ............................................................................... 635

Data Engine Block—CRC Generator/Checker Subblock ..................................................................................... 636

Overview ........................................................................................................................................................ 636

Agere Systems Inc.

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