TCN75(2002) Ver la hoja de datos (PDF) - Microchip Technology
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TCN75 Datasheet PDF : 18 Pages
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TCN75
3.0 DETAILED DESCRIPTION
A typical TCN75 hardware connection is shown in
Figure 3-1.
FIGURE 3-1:
TYPICAL APPLICATION
Address A0
(Set as Desired) A1
A2
I2C™ Interface SDA
SCL
+VDD (3V to 5.5V)
CBypass 0.1µF Recommended
Unless Device is Mounted
Close to CPU
8
7
6
5
3
To Controller
TCN75 INT/CMPTR
1
2
4
3.1 Serial Data (SDA)
Bi-directional. Serial data is transferred in both
directions using this pin.
3.2 Serial Clock (SCL)
Input. Clocks data into and out of the TCN75.
3.3 INT/CMPTR
Open Collector, Programmable Polarity. In Comparator
mode, unconditionally driven active any time
temperature exceeds the value programmed into the
TSET register. INT/CMPTR will become inactive when
temperature subsequently falls below the THYST set-
ting. (See Section 5.0, Register Set and Programmer's
Model). In Interrupt mode, INT/CMPTR is also made
active by TEMP exceeding TSET; it is unconditionally
RESET to its inactive state by reading any register via
the 2-wire bus. If and when temperature falls below
THYST, INT/CMPTR is again driven active. Reading any
register will clear the THYST interrupt. In Interrupt mode,
the INT/CMPTR output is unconditionally RESET upon
entering Shutdown mode. If programmed as an active-
low output, it can be wire-ORed with any number of
other open collector devices. Most systems will require
a pull-up resistor for this configuration.
Note that current sourced from the pull-up resistor
causes power dissipation and may cause internal heat-
ing of the TCN75. To avoid affecting the accuracy of
ambient temperature readings, the pull-up resistor
should be made as large as possible. INT/CMPTR's
output polarity may be programmed by writing to the
INT/CMPTR POLARITY bit in the CONFIG register.
The default is active low.
DS21490B-page 6
3.4 Address (A2, A1, A0)
Inputs. Sets the three Least Significant bits of the
TCN75 8-bit address. A match between the TCN75's
address and the address specified in the serial bit
stream must be made to initiate communication with
the TCN75. Many protocol-compatible devices with
other addresses may share the same 2-wire bus.
3.5 Slave Address
The four Most Significant bits of the Address Byte (A6,
A5, A4, A3) are fixed to 1001[B]. The states of A2, A1
and A0 in the serial bit stream must match the states of
the A2, A1 and A0 address inputs for the TCN75 to
respond with an Acknowledge (indicating the TCN75 is
on the bus and ready to accept data). The Slave
Address is represented in Table 3-1.
TABLE 3-1:
1
0
MSB
TCN75 SLAVE ADDRESS
0
1
A2
A1
A0
LSBS
3.6 Comparator/Interrupt Modes
INT/CMPTR behaves differently depending on whether
the TCN75 is in Comparator mode or Interrupt mode.
Comparator mode is designed for simple thermostatic
operation. INT/CMPTR will go active anytime TEMP
exceeds TSET. When in Comparator mode, INT/
CMPTR will remain active until TEMP falls below
THYST, whereupon it will RESET to its inactive state.
The state of INT/CMPTR is maintained in Shutdown
mode when the TCN75 is in Comparator mode. In
Interrupt mode, INT/CMPTR will remain active
indefinitely, even if TEMP falls below THYST, until any
register is read via the 2-wire bus. Interrupt mode is
better suited to interrupt driven microprocessor-based
© 2002 Microchip Technology Inc.
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