TC9028AP Ver la hoja de datos (PDF) - Toshiba

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componentes Descripción

Fabricante

TC9028AP

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

Toshiba 

TC9028AP/AF

Operation

1. Configuration

(1) Program counter (PC)

(2) Memory bank register (MBR)

(3) Stack register (STACK)

(4) Data counter (DC)

(5) Program memory (ROM)

(6) L register (LR)

(7) Data memory (RAM)

(8) Arithmetic and logic unit (ALU), accumulator

(9) Flags

(10) Clock generator, timing generator

(11) I/O ports

a. Port register (PR)

b. Command register (CR)

(12) Timer counter

a. Timer register (TR)

b. Timer counter output

c. Watch dog timer output

(13) Hold mode control circuit

(14) Reset circuit

Following is a description of the hardware configuration and operation of the components listed above.

2. Internal CPU functions

2.1 Program counter (PC)

The program counter is a 10bit binary counter which holds the program memory address of the next

instruction to be executed.

The program counter is normally incremented for each instruction fetch.

When branch instructions and subroutine instructions are executed, the values specified in Table 2.1

are set. The program counter is initialized to 0 at reset.

Page

Address

within page

00 H

01

0H

3E

3F

00

01

1

3E

3F

00

2 01

Address

000 H

001

03E

03F

040

041

07E

07F

080

081

A 3E

2BE

3F

2BF

00

2C0

01

2C1

B

3E

2FE

3F

2FF

Figure 2.1 Program memory configuration

3

2002-04-19

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