TC9028AP Ver la hoja de datos (PDF) - Toshiba

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Fabricante

TC9028AP

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

Toshiba 

TC9028AP/AF

(3) P5 (P53 to P51) port

Port P5 is a 3bit output port with a latch.

P51 is for P-ch open-drain output. An option allows it to be used for push/pull output. The latch

is initialized to 0 at reset.

P52 is for large current output for driving the send display LED.

The output latch is initialized to 1 at reset.

P53 is for large current output for driving the infrared LED. Resetting the output latch to 1

outputs fosc/12 (duty 1/3) or fosc/8 (duty 1/2) sub-carrier frequency for modulation. An option

allows selection of fosc/24 (duty 1/3) or fosc/16 (duty 1/2) sub-carrier frequency. Sub-carrier

frequency (duty) is selected by the command register. The latch is initialized to 0 at reset.

The LSB (P50) of the port P5 is used for selecting the sub-carrier frequency (duty) output from

P53 using the write-only command register.

The latch is initialized to 0 at reset.

Although port P5 is an output port, when an input instruction is executed, P5 can read

timer/counter output (IT3 to IT0).

Port P5, Command Register (port address OP05) and,

Timer / Counter Output (port address IP05)

3

2

1

0

P53 P52 P51 CR (Initial value: 0100)

IT3 IT2 IT1 IT0

Sub-carrier frequency

0: fosc/12 (duty 1/3)

1: fosc/8 (duty 1/2)

Option

0: fosc/24 (duty 1/3)

1: fosc/16 (duty 1/2)

Figure 3.3 Port P5

3.2 Timer/counter

The timer/counter is a 17 step binary counter used to divide the fundamental clock. It outputs a

pulse with a cycle selected from steps 10 through 15.

The timer/counter is a 17 step binary counter used to divide the fundamental clock. It outputs a pulse

with a cycle selected from steps 10 through 15.

The uses of the timer/counter are listed below. The timer/counter is cleared to 0 at reset, when a timer

reset instruction (TMRST) is executed, and when hold mode is cancelled.

1. Timer generating fc/210 to fc/215 [Hz] pulses

2. Watchdog timer

3. Warming-up timer when hold mode is cancelled

10

2002-04-19

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