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T35L6464A

SYNCHRONOUS BURST SRAM 64K x 64 SRAM

Taiwan Memory Technology 

tm TE

CH

T35L6464A

GENERAL

DESCRIPTION

(ADSC , ADSP ,and ADV ), write enables ( BW1,

BW2 , BW3 , BW4 , BW5 , BW6 , BW7 ,

BW8 and BWE ), and global write ( GW ).

Asynchronous inputs include the output enable

(OE ) , Snooze enable (ZZ) and burst mode control

(MODE). The data outputs (Q), enabled by OE ,

are also asynchronous.

Addresses and chip enables are registered with

either address status processor ( ADSP ) or address

status controller (ADSC ) input pins. Subsequent

burst addresses can be internally generated as

controlled by the burst advance pin (ADV ).

Address, data inputs, and write controls are

registered on-chip to initiate self-timed WRITE

cycle. WRITE cycles can be one to eight bytes

wide

FUNCTIONAL BLOCK DIAGRAM

16

A0-A15

MODE

ADV

CLK

ADSC

ADSP

ADDRESS

16

14

16

REGISTER

A0 A1

DO D1 Q1

BINARY

COUNTER

& LOGIC

LOAD

CLR

A1'

Q0 A0'

(continued)

as controlled by the write control inputs.

Individual byte write allows individual byte to be

written. BW1 controls DQ1-DQ8. BW2

controls DQ9-DQ16. BW3 controls DQ17-DQ24.

BW4 controls DQ25-DQ32. BW5 controls

DQ33-DQ40. BW6 controls DQ41-DQ48.

BW7 controls DQ49-DQ56. BW8 controls

DQ57-DQ64. BW1, BW2 , BW3 , BW4 , BW5,

BW6 , BW7 and BW8 can be active only with

BWE being LOW. GW being LOW causes all

bytes to be written. WRITE pass-through

capability allows written data available at the output

for the immediately next READ cycle. This

device also incorporates pipelined enable circuit for

easy depth expansion without penalizing system

performance.

BWE

BW8

BW7

BW6

BW5

BW4

BYTE 8

WRITE REGISTER

BYTE 7

WRITE REGISTER

BYTE 6

WRITE REGISTER

BYTE 5

WRITE REGISTER

BYTE 4

WRITE REGISTER

8

8

BYTE 8

WRITE DRIVER

8

BYTE 7

8

WRITE DRIVER

8

8

BYTE 6

WRITE DRIVER

8

8

BYTE 5

WRITE DRIVER

8

8

BYTE 4

WRITE DRIVER

64K x 8 x 8

MEMORY

ARRAY

SENSE

AMPS

BW3

BW2

BYTE 3

WRITE REGISTER

BYTE 2

WRITE REGISTER

8

8

BYTE 3

WRITE DRIVER

8

8

BYTE 2

WRITE DRIVER

64

64

OUTPUT

OUTPUT

64

DQ1

REGISTERS

BUFFERS

.

.

.

DQ64

BW1

GW

CE

CE2

CE3

CE2

CE3

OE

BYTE 1

WRITE REGISTER

8

8

BYTE 1

WRITE DRIVER

Chip

Enable

ENABLE

REGISTER

PIPELINED

ENABLE

8

INPUT

REGISTERS

Note: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin

descriptions and timing diagrams for detailed information.

Taiwan Memory Technology, Inc. reserves the right P. 2

to change products or specifications without notice.

Publication Date: AUG. 1998

Revision: E

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